【作者】 薛涛； 朱劲夫； 龚光华； 李荐民；

【Author】 XUE Tao;ZHU Jinfu;GONG Guanghua;LI Jianmin;Dept.of Tsinghua University;

【机构】 清华大学工程物理系；

【摘要】 ZYNQ是全新架构的现场可编程阵列FPGA和高性能双核ARM Cortex-A9处理器的综合体,而核电子学领域的数据读出一直是影响整个数据采集系统的关键。从传统的处理器外加FPGA的双芯片解决方案到目前的ZYNQ单芯片解决方案,不仅能够有效的减小电子学硬件的尺寸和功耗,还能非常大的提高FPGA和处理器之间的有效带宽,为整个读出电子学带来了新的发展。我们在2014年研制了基于ZYNQ XC7Z010的单芯片读出模块,而今年研制了基于ZYNQ XC7Z020的增强型单芯片读出模块,具有更多的IO和LVDS接口以及更丰富的外设接口。本文阐述了基于ZYNQXC7Z020增强型单芯片的读出模块ZYNQBee2的研制细节,包括整个系统架构和传统架构的对比,新架构的硬件设计细节和难点以及相对ZYNQBee版本性能上的提高等。另外还包括了DDR3 SDRAM布线的关键问题的解决,千兆以太网接口以及嵌入式Linux的移植等。更多还原

【Abstract】 ZYNQ is the new all programmable SoC architecture of FPGA with dual-core high performance ARM Cortex-A9 processors from Xilinx. In the application of nuclear electronics, performance of readout is the key problem. From CPU plus FPGA, the traditional two chip readout solution, to one chip solution with ZYNQ, we can reduce not only the footprint and power consumption of electronics, but also we can get more bandwidths between FPGA and CPU, it give more flexibility to nuclear electronics. We develop the ZYNQBee readout module on 2014, which is based on XC7 Z010, and now the new enhanced module based on XC7 Z020 is released. The new ZYNQBee2 module has more IO, LVDS interface and peripherals.This paper will introduce the details of ZYNQBee2’s hardware design, include comparison of traditional architecture and new, improvement between ZYNQBee and ZYNQBee2. Key problem of DDR3 SDRAM layout, Giga Bits Ethernet interface and Embedded Linux will also be discussed.更多还原