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BIST可测性设计的低功耗技术
Low Power Technology of BIST Testability Design
【Author】 Li Jinfeng Wang Ying Xin Xiaoning(Information Engineering School, Shenyang Institute of Chemical Technology, Shenyang 110142, China) (Shenyang Institute of Automation,Chinese Academy of Sciences,Shenyang 110016,China)
【机构】 沈阳化工学院信息工程学院;
【摘要】 在BIST测试过程中,测试电路的加入使得数字系统的功耗明显加大,低功耗的BIST设计得到人们的广泛关注。本文介绍几种BIST的低功耗设计技术,各种方法的综合应用会使系统的功耗指标达到最佳。
【Abstract】 During the BIST testing, power consumption of digital system may increase significantly due to the test circuits. The power of a digital system is considerably higher in test mode than in system mode. In this paper, we present several novel low power BIST design techniques. The integration of several methods utilizing the advantage and remedying the disadvantage will make the low power design of system to optimum.
- 【会议录名称】 首届信息获取与处理学术会议论文集
- 【会议名称】首届信息的获取与处理学术会议
- 【会议时间】2003
- 【分类号】TN407
- 【主办单位】中国仪器仪表学会