【作者】 黄正峰； 梁华国； 陈田； 詹文法； 孙科；

【Author】 Huang Zhengfeng Liang Huaguo Chen Tian Zhan Wenfa Sun Ke (School of Computer and Information,Hefei University of Technology,Hefei 23009,China)

【机构】 合肥工业大学计算机与信息学院；

【摘要】 针对深亚微米工艺下瞬态故障引发的软错误成为芯片失效的主导原因,文中给出一种容软错误的高可靠BIST结构:FT-CBILBO。该结构首先对并发内建逻辑块观察器(CBILBO)进行改进,通过对多输入特征寄存器进行功能复用,构建双模冗余的容错微结构并且能有效降低开销。为了克服双模冗余容错结构仅能检错、无法纠错的缺点,FT-CBILBO在触发器输出端插入C单元,有效针对单事件翻转进行防护,阻塞瞬态故障引发的软错误。本结构在UMC 0.18μm工艺下实验,实验结果表明,面积开销在28.37%～33.29%,性能开销在4.99%～18.20%。更多还原

【Abstract】 With the development of Deep Sub-Micron manufacturing process,soft error caused by transient faults has become the predominant issues for chip failures.This paper proposes a soft-error-tolerant high reliable BIST structure:FT-CBILBO.As an evolution of CBILBO,FT-CBILBO reuses MISR to construct DMR fault-tolerant scheme to reduce the overhead.FT-CBILBO can block soft error by inserting C-Element so as to tolerant SEU.FT-CBILBO is implemented in UMC 0.18μm process.The experiment results show that area overhead is ranging from 28.37% to 33.29%,and performance overhead is ranging from 4.99% to 18.20%.更多还原