改进的过程、位平面双重并行分数位平面编码

【作者】 韩彦菊； 许超； 张益贞；

【机构】 北京大学视觉与听觉信息处理国家重点实验室2108室；

【摘要】 分数位平面编码是JPEG2000图像压缩国际标准中的核心技术之一,是影响JPEG2000编码速度的最关键部分。已有的位平面、过程双重并行(BPDP)的编码方法,可以大幅度提高编码速度。但是,加快编码速度的代价是电路结构复杂化、电路资源增加.本文提出一种改进的位平面、过程双重并行编码的电路结构,它在提高编码速度的同时,可以大幅度降低电路消耗,减少溢出周期,从而简化与后续算术编码器(AE)的接口。与BPDP相比,逻辑电路减少近45%,溢出周期平均降低约10%.更多还原

【Abstract】 Fractional bit-plane coding (FBP) is one of nuclear technologies in JPEG2000 systems and the most critical part to influence the coding speed. There are bit-plane and pass dual parallel methods that can speed up the encoding, but the acceleration is always companied with the complication of the circuit structure and the increase of the circuit resources. In this paper, we present an improved bit-plane and pass dual parallel architecture (I3PDP), which not only achieves a high encoding speed but also reduces the logic circuit requirement and the coding delay. The interface with AE is simplified. Experimental results show that about 45% of the logic circuit is reduced and that the average fall of the delay per code-block is 10% compared with BPDP.更多还原