【作者】 周小康； 王继安； 庞世甫； 李威； 龚敏；

【Author】 Zhou Xiao-kang, Wang Ji-an, Pang Shi-fu, Li Wei, Gong Min Key lab of microelectronics, School of Physical Science and Technology, Sichuan University, 610064 The College of Microelectronics and Solid-State Electronics, 610054

【机构】 微电子技术四川省重点实验室四川大学物理科学与技术学院； 电子科技大学微电子与固体电子学院；

【摘要】 本文设计了一种用于高速流水线ADC的时钟管理器,该电路以延迟锁相环(DLL)电路为核心,由偏置电路、时钟输入电路、50％占空比稳定电路和无交叠时钟电路构成。该电路用0．35um BiCMOS工艺条件下cadence spectre仿真, 由测量结果可知,时钟管理器可以实现70MHz-300MHz有效输出。在250MHz典型频率下测得峰值抖动为16ps,占空比为50％,功耗为47mW。仿真结果表明该时钟管理器具有高速度、高精度、低功耗的特点,适用于高速流水线ADC。更多还原

【Abstract】 A kind of clock management circuit, which used in high-speed pipeline ADC, was designed. The clock management circuit with DLL as its core cell consists of bias circuit, clock input circuit, 50%duty-cycle stabilizing circuit and no-overlap output circuit. The circuit is based on a 0.35um Bi CMOS process. The measured results have shown the DLL exhibits a lock range of 70MHz-300MHz while the peak-to-peak jitter, duty-cycle and power dissipation is 16ps, 50% and 47mW at 250MHz. That is, this clock management circuit has the characteristics with high speed, good precision and low power dissipation. It’s suitable for the high-speed pipeline A/D converter.更多还原