【作者】 胡蓉彬； 王继安； 庞世甫； 朱鹏； 李威； 龚敏；

【Author】 Hu Rong-Bin Wang Ji-an Pang Shi-fu Li Wei Gong Min (Key lab of microelectronics of the province, School of Physical Science and Technology Sichuan University, 610064,China) (The College of Micro-electronics and Solid-state Electronics University of Electronic Science and Technology of China, Chengdu, 610054)

【机构】 微电子技术四川省重点实验室四川大学物理科学与技术学院； 电子科技大学微电子与固体电子学院；

【摘要】 本文用CMOS反相器作比较器设计了一个3位的高速低功率flash ADC核。该ADC核可以应用到分级型和流水线型结构的ADC中实现更高的转换位数。该3位ADC核采用Choudhury等人提出的编码方案。解决了高速ADC的编码电路问题。采用SMIC的0．35um／3．3CMOS工艺模型,用Candence软件进行仿真,该3位ADC速度高达2Gsps,在该速度下具有 0．56mW的低功率。更多还原

【Abstract】 In this paper, a 3-bit low-power ADC core has been designed using CMOS inverter. The 3-bit ADC core can be used in muti-stage ADC and pipeline ADC to achieve higher resolution. In the design of the 3-bit ADC, the encoding scheme proposed by Choudhury et al. was used to solve the problem of encoding circuit of high-speed ADC. Simulated results using Cadence’s EDA software with 0.35um/3.3 CMOS model of SMIC have shown that the speed of the 3-bit ADC could achieve 2Gsps. At this speed, the power consumption of the ADC was only 0.56mW.更多还原