【作者】 陈红卫； 吴建辉；

【Author】 Chen Hongwei Wu Jianhai (Southeast University Nanjing 210096)

【机构】 东南大学；

【摘要】 本文提出了一种新型的基于运算放大器的开关电容采样保持电路结构。采用速度补偿解决了高速高分辨采样保持电路对放大器要求增益高和速度快之间的矛盾。具体设计了采样保持电路。用Chart 0.35μmCMOS工艺,进行HSPICE仿真,结果表明,本文设计的采样保持电路的分辨率为10位,采样速率高于70MHz/S。更多还原

【Abstract】 The paper introduces a new sample-and-hold circuit based on operational amplifier. It is useful to solve the conflict between speed and DC gain of an amplifier in high-speed and high-resolution sample-and-hold circuit to use a speed compensation circuit. The circuit is simulated by 0.35μm CMOS technology. The sample rate can achieve higher than 70Mhz per second and the resolution is 10bits.更多还原