【作者】 欧阳一鸣； 刘蓓； 齐芸；

【Author】 Ouyang Yiming,Liu Bei,Liang Huaguo (School of Computer and Information Hefei University of Technology Hefei 230009 China)

【机构】 合肥工业大学计算机与信息学院；

【摘要】 三维集成电路具有比传统的平面集成电路更高的性能.在三维集成电路上进行有效的测试架构设计和优化技术可以减少集成电路的测试代价.提出了一种三维片上网络测试的时间优化解决方案.首先根据封装前的IP核测试时间,为各层芯片选择合适的IP核,使得每层芯片上的IP核总的测试时间最接近;再利用整数线性规划和随机舍入的方法,在总的数据位宽限制下,再次为每层芯片分配合适的TAM数据线宽度,进一步减小各层芯片上IP核的测试时间.在ITC’02标准下得到的实验结果可以看出,3DNoC的测试时间与2DNoC的测试时间相比有了大幅度的降低.更多还原

【Abstract】 Three dimensional(3D) integrated circuits(ICs) are capable of achieving better performance compared to more traditional planar ICs.Effective test architecture design and optimization techniques are essential to minimize the test cost in 3D IC.A test solution for 3D Network-on-Chip(NoC) with test time optimization is presented.Firstly we select the appropriate IP cores for each layer according to the test time of unwrapped cores in order to balance the test time of IP cores on each layer.Secondly we use integer linear programming(ILP) and random rounding method to allocate TAM bit-width for each layer under the constraints of the total TAM bit-width.Then we can reduce the test time of IP cores on each layer further.Simulation results are presented for ITC’02 Test Benchmarks that the test time for 3D NoC has been reduced significantly compared to the test time for 2D NoC.更多还原