【作者】 范兵； 刘岩； 华斯亮； 王东辉； 侯朝焕；

【Author】 FAN Bing,LIU Yan,HUA Si-liang,WANG Dong-hui,HOU Chao-huan 1.Institute of Acoustics,Chinese Academy of Sciences,Beijing 100190,China 2.Graduate University,Chinese Academy of Sciences,Beijing 100190,China

【机构】 中国科学院声学研究所； 中国科学院研究生院；

【摘要】 基于预放大锁存快速比较理论,采用开关电容电路,设计了一种适用于高速低功耗模数转换器(ADCs)的电荷分配型全差分CMOS动态比较器。比较器由开关电容网络、预放大器、锁存器和输出缓冲器构成,在两个相互不交叠的时钟控制下工作。通过在预放大器和锁存器之间加入隔离电路,并采用中和技术(neutralization),以减轻回馈(kickback)对输入信号的影响。采用典型的0.18μm/1.8V CMOS工艺模型,用Cadence软件仿真,比较器在时钟频率为100MHz时,输入动态范围为1V,回馈噪声在信号输入端引入的动态失调为8.2mV,功耗约为102.6μW。更多还原

【Abstract】 A full differential dynamic comparator is designed based on the preamplifier-latch fast-compare theory and by using switched-capacitor circuits.It is applicable to high-speed,low-power pipeline ADC modules. The proposed comparator consists of a preamplifier,a latch stage and output buffer.In the comparator offset cancellation is used to reduce the influence of the kickback noise.Simulation results based on standard CMOS 0.18μm/1.8 V technology show that,the input dynamic range is 1 V,input referred dynamic offset is less than 8.2 mV,and the power dissipation is 102.6μW at 100 MHz.更多还原