【作者】 郝庭基； 尹长川； 罗涛； 刘丹谱；

【Author】 Hao Tingji,Yin Changchuan,Luo Tao,Liu Danpu(Key Laboratory of Universal Wireless Communications,Ministry of Education,Beijing University of Posts and Telecommunications,Beijing100876,China)

【机构】 北京邮电大学泛网无线通信教育部重点实验室；

【摘要】 提出了一种长期演进(longtermevolution,LTE)系统帧定时同步的低复杂度现场可编程门阵列(field-programmablegatearray,FPGA)实现方案,通过对接收信号低通滤波并下采样之后进行主同步序列(primarysynchronizationsignal,PSS)的检测和半帧定时,之后提取接收辅同步序列(secondarysynchronizationsignal,SSS)进行解调之后的相关检测,得到帧定时位置和小区标识,最后通过跟踪维持下行链路的同步。理论分析和仿真结果表明,本文提出的方案能够在不影响帧定时性能的情况下,有效降低FPGA的资源占用,并将PSS检测的处理时延降低至传统算法的1/64。更多还原

【Abstract】 In this paper we investigate a kind of low complexity FPGA(field-programmable gate array) implementation scheme of frame timing synchronization in LTE(long term evolution) systems.The proposed algorithms process received baseband signals with low pass filtering and down-sampling then perform PSS(primary synchronization signal) detection and half frame timing.Next,SSS(secondary synchronization signal) demodulation and detection are made to get frame timing and cell physical identity.Finally,it is necessary to track and maintain downlink synchronization status.Theoretical analysis and simulation results show that the scheme proposed here could effectively reduce FPGA logical resource and PSS detection processing duration to 1/64 of traditional algorithm,without the decline of frame timing synchronization performance.更多还原