【作者】 刘世虎； 窦建华；

【Author】 Shihu Liu,Jianhua Dou School of Computer and Information,Hefei University of Technology,Hefei,China

【机构】 合肥工业大学计算机与信息学院；

【摘要】 本文以FPGA为平台介绍了一款由改进Gold序列和全数字锁相环组成的跳频器,它能将输入的跳频频率族中的呈伪随机跳变的频率信号在跳频周期的开始阶段快速捕获并锁定,然后得到稳定输出。采用verilog语言完成系统功能模块和总体编程,并且在QuartusII平台和Modelsim平台分别完成系统后仿真。结果表明,输入中心频率在短波频段内的信号,可以在数微秒到十数微秒内锁定,与普通集成锁相环芯片相比,锁定时间可提高两个数量级以上。更多还原

【Abstract】 In this paper,it is presented that a frequency-hopper is composed of the improved Gold-sequence and the ADPLL on the FPGA platform,at the beginning of a hopping cycle which can quickly capture as well as lock every pseudo-random hopping frequency belonging to the hopping frequencies family,and generate the stable outputs.The verilog-codes of the system and its functional modules succeed separately in compilation and simulation on the Quartus II and Modelsim platform.The results demonstrate that for the input center frequencies in the shortwave the re-locking times are between several and twenty microseconds,compared with the common integrated PLL chip,and advancing beyond two orders of magnitude.更多还原