【作者】 孙志新； 李开航；

【Author】 Zhixin SUN,Kaihang LI Physic Department of Xiamen University,Xiamen,China,361005

【机构】 厦门大学物理系；

【摘要】 设计一种用于流水式A/D转换器的高性能低功耗采样保持电路。该电路采用全差分套筒式增益自举运算放大器和栅压自举电路,电路在TSMC 0.13um CMOS工艺3.3V电源下实现,静态功耗为7.7mw,在奈奎斯特频率下采样频率为100MHZ,输入信号为10MHZ时,达到96.3dB的SFDR,有效位数达到13位。更多还原

【Abstract】 Design of a hight performance low power sample and hold circuit used in pipeline Analog to Digital Converter(ADC).This circuit is based on TSMC 0.13um CMOS technology and 3.3V power supply.The circuit uses a fully differential telescopic gain-boosted operational amplifier circuit,and a gate voltage bootstrapped switch circuit is employed to meet the requirements.The circuit consumes only 7.7 mw static power and it can attain 96.3 dB Spurious Free Dynamic Range(SFDR)when the input signal is 10MHZ and Nyquist frequency with sampling rate of 100 MS/s,of which the effective number of bit(ENOB)can reach to 13 bit.更多还原