【作者】 杨帆；

【导师】 张贺秋； 周泉；

【作者基本信息】 大连理工大学 ， 集成电路工程， 2025， 硕士

【摘要】 时间数字转换器(Time-to-digital Convert,TDC)能够将模拟的时间或相位信号转变为可用于数字信号处理的数字信号,其用于测量两个不同脉冲信号之间的时间/相位差。随着CMOS半导体工艺技术的快速发展,TDC的各项性能指标也得到了快速的发展。由于它具有的许多优势,因此其在激光测距、医学、电子测量和高能物理等工程和科研领域被广泛应用。然而,现有的TDC结构多以单段式或两段式结构为主,如在需要高精度的情况下,一般要求TDC的分辨率能够达到皮秒级别精度,而此时TDC的测量范围却只能够做到纳秒级别,所以想要同时满足高精度和高测量范围的要求一直是困扰TDC设计的一大技术难题,也是其以后的发展趋势。本文针对目前TDC研究中的技术瓶颈点和发展的趋势以及机器人视觉识别应用中的需求,基于现有TDC的组合结构,提出了基于延时锁相环(Delay-Locked Loop,DLL)的高精度、高测量范围的四通道TDC的电路架构,该TDC为四段TDC结构,主要包括COUNTER级TDC、MSB级TDC、LSB级TDC和LLSB级TDC。其中,COUNTER级TDC采用异步计数器架构,使用时钟周期10ns作为分辨率,实现高测量范围;MSB级TDC采用单延时链TDC架构,采用64项的多项时钟,以156.25ps作为分辨率处理COUNTER级TDC的余量;LSB级TDC采用单延时链TDC架构,采用32项的多项时钟,以9.76ps作为分辨率处理MSB级TDC的余量;LLSB级TDC采用阵列型并行缩放型TDC架构,用来实现子门延时的高分辨率。此外,本论文的TDC采用DLL电路提供基准电压,因此不需要其他的校准电路就能满足TDC在高频情况下对高精度和高稳定性的要求。本设计采用TSMC 65nm标准CMOS工艺,通过Cadence Virtuoso工具完成电路的设计、版图绘制、电路仿真及流片工作,一个TDC通道和DLL加起来的面积为0.76mm~2。通过对芯片成品进行测试可知:本文实现的TDC在基准时钟100MHz的条件下,实现了9.76ps的分辨率,同时DNL为5.32ps,INL为8.63ps,并具备2.56μs的动态范围,死区时间低于13ns。与其他的TDC相比,本文设计的TDC在保持了高精度的情况下,极大的拓宽了TDC的测量范围。更多还原

【Abstract】 TDC can convert analog time or phase signals into digital signals for digital signal processing,which is used to measure the time/phase difference between two different pulse signals.With the rapid development of CMOS semiconductor technology,the performance indicators of TDC have also been developed rapidly.Because of its many advantages,it is widely used in engineering and scientific research fields such as laser ranging,medicine,electronic measurement and high-energy physics.However,the existing TDC structures are mostly single segment or two segment structures.For example,when high accuracy is required,the resolution of TDC is generally required to reach the picosecond accuracy,while the measurement range of TDC can only reach the nanosecond.Therefore,to meet the requirements of high accuracy and wide measurement range at the same time has always been a major technical problem puzzling TDC design,and it is also its future development trend.Aiming at the technical bottlenecks and development trends in the current TDC research,as well as the requirements in the application of robot visual recognition,based on the combination structure of the existing TDC,this paper proposes a circuit architecture of four channel TDC with high accuracy and high measurement range based on the DLL.The TDC is a four segment TDC structure,mainly including COUNTER TDC,MSB TDC,LSB TDC and LLSB TDC.Among them,COUNTER TDC adopts asynchronous counter architecture and uses the clock cycle of 10ns as the resolution to achieve a high measurement range;MSB TDC adopts single delay chain TDC architecture,adopts 64 item multi clock,and uses 156.25ps as the resolution to process the margin of COUNTER TDC;LSB TDC adopts single delay chain TDC architecture,adopts 32 item multi clock,and uses 9.76ps as the resolution to process the margin of MSB TDC;LLSB TDC adopts array parallel scaling TDC architecture to achieve high resolution of sub gate delay.In addition,the TDC in this paper uses DLL circuit to provide reference voltage,so no other calibration circuit is required to meet the requirements of TDC for high accuracy and stability in high-frequency situations.This design adopts TSMC 0.65μm standard CMOS process,and completes the circuit design,layout drawing,circuit simulation and streaming work through Cadence Virtuoso tool,with an area of 0.76 mm2.Through the test of the finished chip,it can be seen that the TDC realized in this paper achieves a resolution of 9.76ps under the condition of 100MHz reference clock,while the DNL is 5.32ps,INL is 8.63ps,and has a dynamic range of 2.56μs,and the dead time is less than 13ns.Compared with other TDCs,the TDC designed in this paper has greatly widened the measurement range of TDC while maintaining high accuracy.更多还原