【作者】 高杰；

【导师】 邓红辉；

【作者基本信息】 合肥工业大学 ， 集成电路工程（专业学位）， 2024， 硕士

【摘要】 模数转换器(Analog-to-Digital Converter,ADC)作为连接自然界和数字世界的桥梁,在信号处理系统中具有重要地位。在无线通信和工业控制等领域,设备要实时处理各项任务,同时还要有出色的续航能力以确保长时间的稳定工作,这就要求ADC既要有较快的速度,又要有较低的功耗。流水线ADC(Pipelined ADC)具有高速高精度的优势,但其功耗较大,无法满足低功耗的应用需求。逐次逼近型ADC(SAR ADC)功耗较低,但受限于逐次逼近的量化方式,其速度较慢。作为两者相结合的混合型架构,流水线逐次逼近型ADC(Pipelined-SAR ADC)能够同时实现高速和低功耗的性能,因此成为了近年来的研究热点。本文以高速低功耗Pipelined-SAR ADC为研究对象,首先调研了国内外Pipelined-SAR ADC的研究现状,然后分析了Pipelined-SAR ADC的原理和误差。综合考虑速度、功耗、精度后采用了首级分辨率为8,第二级分辨率为6,带2位级间冗余位的两级结构来实现12位的总分辨率。最后,对12位100MSPS Pipelined-SAR ADC的两级子SAR ADC和余量放大器进行了电路设计。针对传统结构中ADC整体速度受总分辨率限制以及第一级SAR ADC工作周期中的放大相造成了时序冗余这两个问题,本文设计了一种双电容阵列和部分交织技术相结合的高速子级结构以突破速度限制。该结构通过一个小DAC快速量化并按照时间交织的方式驱动两个大DAC轮流翻转产生余量电压,加快了子级的量化速度并去除了第一级SAR ADC工作周期中的放大相,有效提升了整体ADC的速度性能。针对该结构中多条采样路径采样时间失配所带来的误差,本文设计了2位级间冗余位以提供更大的误差容忍范围,防止其影响ADC的量化结果。在余量放大器方面,采用交叉耦合cascode动态放大器作为余量放大器,在保持低功耗的同时实现了16倍的高增益需求。采用单极点放大器来控制动态放大器的放大时间,以保证在PVT变化下动态放大器的增益稳定,并结合前台校准电路对动态放大器的尾电流进行调节,进一步降低动态放大器的增益误差,从而保证ADC的精度。本文基于TSMC 180nm CMOS工艺,设计了一款12位分辨率,100MS/s采样率的两级Pipelined-SAR ADC,通过仿真结果表明,在电源电压为1.8V,输入正弦波信号频率为49.609375MHz的情况下,级间增益校准前ADC的有效位数为9.54bit,无杂散动态范围为75.63d B,校准后ADC的有效位数提升到了11.0bit,无杂散动态范围提升到了80.6d B。ADC核心功耗仅为7.19m W,实现的Fo M值为35.1f J/conv-step。更多还原

【Abstract】 Analog to Digital Converter(ADC)plays an important role in signal processing systems as a bridge connecting nature and the digital world.In fields such as wireless communication and industrial control,devices need to process various tasks in real-time,while also having excellent endurance to ensure long-term stable operation.This requires ADCs to have both fast speed and low power consumption.Pipelined ADCs have the advantage of high speed and precision,but their high power consumption cannot meet the requirements of low-power applications.SAR ADC has lower power consumption,but is limited by the quantization method of sequential approximation,resulting in slower speed.As a hybrid architecture combining the two,Pipeline SAR ADC has become a research hotspot in recent years due to its ability to achieve both high-speed and low-power performance simultaneously.This thesis focuses on high-speed and low-power Pipelined SAR ADCs.Firstly,the research status of Pipelined SAR ADC at home and abroad is investigated,and then the principle and error of Pipelined SAR ADC are analyzed.After considering speed,power consumption,and accuracy,a two-stage structure with a first level resolution of 8 and a second level resolution of 6,with 2-bit inter level redundant bits,was adopted to achieve a total resolution of 12 bits.Finally,the circuit design was carried out for the two-stage sub SAR ADC and residual amplifier of a 12 bit 100MSPS Pipelined SAR ADC.In order to solve the problem that the overall ADC speed is limited by the total resolution and the time sequence redundancy caused by the amplification phase in the working cycle of the first-stage SAR ADC,this thesis designs a high-speed sub-structure that combines the dual-capacitor array and partial interweaving technology to break through the speed limit.This structure utilizes a small DAC for fast quantization and drives two large DACs to flip over in a time interleaved manner to generate residual voltage,accelerating the quantization speed of the sub stages and removing the amplification phase in the first stage SAR ADC working cycle,effectively improving the overall speed performance of the ADC.In response to the errors caused by the sampling time mismatch of multiple sampling paths in this structure,this thesis designs a 2-bit inter stage redundant bit to provide a larger error tolerance range and prevent it from affecting the quantization results of ADC.In terms of residual amplifier,a cross coupled cascode dynamic amplifier is used as the residual amplifier,achieving a high gain requirement of 16 times while maintaining low power consumption.This thesis uses a single pole amplifier to control the amplification time of the dynamic amplifier to ensure stable gain under PVT changes.Combined with the front-end calibration circuit,the tail current of the dynamic amplifier is adjusted to further reduce the gain error of the dynamic amplifier and ensure the accuracy of the ADC.This thesis is based on the TSMC 180nm CMOS process and designs a two-stage Pipelined-SAR ADC with a 12 bit resolution and a sampling rate of 100MS/s.The simulation results show that under the power supply voltage of 1.8V and the input sine wave signal frequency of 49.609375MHz,the ENOB of the ADC before inter stage gain calibration is 9.54 bits,and the SFDR is 75.63d B.After calibration,the ENOB of the ADC is increased to 11.0 bits,and the SFDR is increased to 80.6d B.The core power consumption of ADC is only 7.19m W,and the achieved Fo M value is 35.1f J/conv-step.更多还原