【作者】 张春华；

【导师】 郭春炳；

【作者基本信息】 广东工业大学 ， 通信工程（专业学位）， 2023， 硕士

【摘要】 Sigma-Delta ADC能达到很高的精度和能效比从而在高保真音频设备、中高精度宽带通信系统和低功率生物检测等领域有广泛的应用。Sigma-Delta ADC包括Sigma-Delta调制器和数字滤波器,其中调制器是Sigma-Delta ADC中极为重要的模块,对其整体性能有着至关重要的影响,高性能Sigma-Delta调制器的研究一直都是ADC研究的热点内容。本论文创新设计了一种基于动态接入反相器的新型动态积分器电路和一种基于FVF的三环路LDO电路,并根据自顶向下的设计方法完成了一款16 Bit 3阶1比特CIFF Sigma-Delta调制器电路的设计。论文首先介绍了ADC和Sigma-Delta ADC的基本原理,同时简要讨论了几种基本的调制器结构。分析了各种电路非理想因素并且完成了其Simulink模型设计,同时设计了包含电路非理想效应的调制器的Simulink模型,通过仿真确定了各模块电路的性能指标,并且验证所选的Sigma-Delta调制器结构的电路实现设计指标的可行性,同时基于Simulink设计了相应的数字滤波器。本论文在传统的基于反相器的动态偏置积分器电路中添加了动态接入支路,构成了一种基于动态接入反相器的积分器电路,此动态积分器电路能以较低的功耗得到较快的积分速度,为了降低整体调制器的功耗,将此动态积分器电路用于实现调制器电路的第二、三级积分器。同时设计了一种基于FVF的三环路LDO电路为调制器电路提供共模电平,在LDO电路中加入AC耦合环路和瞬态响应增强电路,提升了LDO电路的响应速度。静态的折叠式共源共栅放大器电路被用于实现调制器的第一级积分器的放大器,并加入斩波技术减小积分器的输入失调电压和输入等效噪声。同时设计了单比特量化器电路和两相不交叠时钟产生电路为调制器的积分器和量化器等电路提供时钟信号。本论文通过Cadence Virtuoso软件完成了调制器的原理图和版图设计,调制器整体电路版图面积为0.6mm~2,最终完成了调制器电路版图的后仿真,当采样频率为256KHz,信号带宽为1KHz时,调制器电路的SNDR为102.4d B,ENOB为16.71Bit,电源电压为1.8V,功耗为100μW,后仿真结果满足设计指标,同时仿真结果表明本论文设计的调制器电路以较低的功耗代价得到了较高的信噪比性能。更多还原

【Abstract】 Sigma-Delta ADC can achieve high resolution and high energy efficiency,so it is widely used in high-fidelity audio equipment,medium-high resolution broadband communication systems,low-power biological detection and other fields.Sigma-Delta ADC is mainly divided into a Sigma-Delta modulator and a digital filter.The Sigma-Delta modulator has a vital impact on the performance of Sigma-Delta ADC.The design of high-performance Sigma-Delta modulator has always been the research focus of ADC.A new dynamic integrator circuit based on a dynamic switch inverter and a three-loop LDO circuit based on FVF are innovatively designed in this thesis.And according to the top-down design process,this thesis designs a 16-bit 3^rd-order 1-bit CIFF Sigma-Delta modulator circuit.The basic principles of ADC and Sigma-Delta ADC are firstly introduced in the thesis,and the several basic Sigma-Delta modulator structures are briefly discussed.The non-ideal model of the circuit is established in the Simulink,and the non-ideal behavior level model of the Sigma-Delta modulator is used to determine the performance index of each module circuit.The feasibility of the selected Sigma-Delta modulator structure circuit implementation is verified by the non-ideal Sigma-Delta modulator Simulink model.At the same time,corresponding digital filters are designed based on Simulink.A dynamic current switch branch is added to the traditional dynamic biased inverter-based integrator circuit and forming a dynamic integrator circuit based on a dynamic current switch inverter.The dynamic integrator circuit proposed in this thesis can obtain faster integration speed with low power consumption.The second and third order integrator of the Sigma-Delta modulator is implemented by the dynamic current switch integrator to reduce the power dissipation of the overall modulator.A tri-loop LDO circuit based on FVF is designed to provide a common mode voltage level for the modulator circuit,and an AC-coupled loop and transient response enhancement circuit are added to improve the transient response speed of the LDO circuit.The amplifier in the first order integrator of the modulator circuit adopted by folded cascode amplifier,and the chopper stabilization technology is used to reduce input offset voltage and input-referred noise of the first stage integrator.A single-bit quantizer and a two-phase non-overlapping clock generation circuit are designed in this thesis,and the clock generation circuit is provided clocks for integrators and quantizer of the modulator.The schematic and layout of the modulator are designed in this thesis through Cadence Virtuoso.The overall circuit layout area of the modulator is 0.6mm².Finally,the layout simulation results show that the prototypeΣ-Δmodulator achieves 102.4d B SNDR,16.71Bit ENOB in a 1KHz signal BW at a sampling frequency of 256KHz,while consuming 100-μW at 1.8V supply.The layout simulation results meet the design index requirements,and the simulation results also indicate that the modulator circuit designed in this thesis achieves high signal-to-noise ratio performance at a lower power consumption.更多还原