【作者】 陈鹏；

【导师】 孟凡计；

【作者基本信息】 电子科技大学 ， 电子信息（专业学位）， 2025， 硕士

【摘要】 无线通信技术的快速发展使电磁环境日益复杂多变,高频谱密度和高动态时变的诸多电磁信号使维护电磁空间安全面临严峻挑战,针对未知方位辐射源的频谱监测和测向有助于发现有潜在危险的干扰源。传统的无线电测向结构多为基于相位比较的相干接收机,受限于瑞利准则约束和未能利用极化信息的影响,其测向精度和多信号监测能力相对不足。针对无线电监测和测向需求,本文设计了一款30～3000MHz宽带矢量测向系统接收前端,采用二次变频超外差架构,一中频3540MHz,二中频135MHz,采样频率可配置。接收前端由接收链路、本振源和采样电路组成,测向结构基于空间谱估计测向,应用场景为应用于测向的六通道接收机,经采样后的数据阵列可用于空域参数估计。本文的主要工作如下:1.根据对无线电测向方法及国内外相关测向产品的分析,明确接收前端的测向方法和应用场景。比较各类接收机典型架构特点,综合测向指标需求,选用二次变频超外差结构,并进行电路模块划分和指标拆解。2.基于链路架构进行射频频率规划和增益分配,根据各模块的指标比较并确定各电路芯片选型,使接收前端满足本振抑制、谐波抑制等指标,选用多级增益调节器件改善接收前端动态范围,利用ADS软件对各电路模块进行S参数仿真,验证电路选型。3.通过对频率源基本类型的分析比较,最终选取双级PLL级联结构,设计了一款3.57～6.54GHz的宽带小步进频率源,可变参考源的加入使锁相环可有效规避整数边界杂散,频率步进100k Hz,相位噪声≤-90d Bc/Hz@1k Hz,杂散抑制≥60d Bc;基于同步采样的客观需求,选取多块型号一致的高速ADC进行采样,利用低相噪锁相环和功分器组为各ADC芯片提供同步低抖动时钟(低于0.3ps)。4.完成矢量测向接收前端的原理图和版图设计,编写各程控器件驱动程序并对各模块进行测试,增益≥65d B,本振抑制≥60d Bc,谐波抑制≥70d Bc。实现了基于STM32的射频前端增益分配、频率切换等功能的程控。本文研制的宽带矢量测向系统接收前端可配合不同的测向天线和信号处理模块,实现无线电监测和测向的功能,具有一定的应用空间。更多还原

【Abstract】 The rapid development of wireless communication technologies has led to an increasingly complex and dynamic electromagnetic environment.The presence of numerous electromagnetic signals characterized by high spectral density and time-varying dynamics poses significant challenges to maintaining the security of the electromagnetic spectrum.Spectrum monitoring and direction finding of unknown radiation sources are essential for identifying potentially hazardous interference sources.Conventional radio direction-finding architectures predominantly adopt coherent receivers based on phase comparison.However,their direction-finding accuracy and capability to monitor multiple signals are limited by the Rayleigh resolution criterion and the failure to exploit polarization information.To address the demands of radio monitoring and direction finding,a broadband vector direction-finding receiver front-end covering the 30–3000 MHz range has been developed.A dual-conversion superheterodyne architecture is employed,featuring an intermediate frequency(IF)of 3540 MHz for the first stage and 135 MHz for the second,with a configurable sampling rate.The receiver front-end consists of the receiving chain,local oscillator sources,and sampling circuitry.The direction-finding structure is based on spatial spectrum estimation and is designed for a six-channel receiver intended for direction-finding applications.The sampled data array can be used for spatial parameter estimation.The main contributions of this work are as follows:1.Based on a comprehensive analysis of radio direction-finding techniques and related products both domestically and internationally,the direction-finding method and application scenarios of the receiver front-end are defined.Various receiver architectures are compared in terms of their characteristics,and a dual-conversion superheterodyne architecture is selected according to direction-finding performance requirements.Circuit modules are partitioned and performance specifications are delineated accordingly.2.RF frequency planning and gain allocation are carried out based on the link architecture.Circuit components are selected by comparing the specifications of each module to ensure compliance with requirements such as local oscillator suppression and harmonic rejection.Multi-stage gain control devices are employed to enhance the dynamic range of the receiver front-end.S-parameter simulations of each circuit module are conducted using ADS software to validate component selection.3.Through a comparative analysis of basic frequency source architectures,a cascaded dual-phase-locked loop(PLL)design is adopted.A broadband frequency source operating from 3.57 GHz to 6.54 GHz with fine tuning steps is developed.The use of a variable reference source enables the PLL to effectively avoid integer-boundary spurs,achieving 100 k Hz frequency steps,phase noise≤-90 d Bc/Hz@1 k Hz,and spurious suppression≥60 d Bc.To meet the requirements of synchronous sampling,multiple high-speed ADCs of the same model are selected.A low phase noise PLL and a power splitter network are used to provide all ADC chips with synchronized,low-jitter clock signals(below 0.3 ps).4.The schematic and layout design of the vector direction-finding receiver front-end is completed.Control programs for various programmable devices are developed,and each module is tested.The receiver front-end achieves a gain of≥65 d B,local oscillator suppression of≥60 d Bc,and harmonic suppression of≥70 d Bc.Programmable control of RF front-end functions such as gain distribution and frequency switching is implemented using an STM32 microcontroller.The broadband vector direction-finding receiver front-end developed in this study can be integrated with various direction-finding antennas and signal processing modules to realize radio monitoring and direction-finding functions,demonstrating promising application potential.更多还原