【作者】 王磊；

【导师】 樊华；

【作者基本信息】 电子科技大学 ， 电子信息（专业学位）， 2025， 硕士

【摘要】 电源管理芯片作为各类电子设备的核心供电单元,其性能直接决定了电子产品的整体表现。本文基于四开关管架构设计升降压（Buck-Boost）DC-DC转换器,采取重载PWM调制、轻载Burst Mode调制和四工作模式策略以及电压模式控制方式。其中主要通过调整单周期的工作模式,降低系统轻载时静态工作电流,从而提高芯片在全负载范围内的转换效率。本文的研究内容主要包括以下三个方面:首先,设计内部带隙基准电路,通过设置基准电压产生模块中产生ΔV_BE的重复单元个数,实现输出基准电压值的灵活可调;调整I_PTAT、I_CTAT的输入比例,使基准电压温度系数接近零,实现输出基准电压低温漂的功能;设计分段温度补偿电路,显著提升其温度特性,仿真结果显示温漂系数为1.56 ppm/℃;多个ΔV_BE的重复单元在一定程度上可以通过统计平均效应显著降低系统的随机失配,仿真结果显示精度达到99.5%。其次,设计内部低压差线性稳压器电路,设计两级运算放大器,显著提高了LDO环路增益,低频增益可达150d B;设计瞬态增强电路,有效抑制输入电压变化与负载瞬态变化对输出电压的影响;设计可编程修调电阻网络R_trim,应对在不同工艺角下输出电压的偏差,修调步长可达0.77m V,显著提高输出电压精度;设计环路补偿网络,提高低压差线性稳压器电路的环路稳定性。最后,设计应用于轻载模式的低阈值比较电压生成电路、电感电流峰值电流检测电路、电感电流反向检测电路。在Burst Mode调制模式下,降低开关频率,减少开关次数;同时,使芯片的一些模块处于休眠状态,降低芯片的静态电流;低阈值比较电压和较少的检测次数可进一步减少功耗,从而系统在轻载工作条件下的转换效率大大提升,最大提升幅度可达2.8倍。根据以上研究,采用0.18μm BCD工艺,使用Cadence Virtuoso软件对各子模块及整体电路进行仿真。完成版图设计与流片后,对芯片进行测试验证了其性能。测试结果表明,系统工作输入电压范围为2.7 V至40 V,稳定输出电压5 V;在重载条件下,各工作模式下的输出电压纹波不超过144.3 m V;在轻载条件下,各工作模式下的输出电压纹波不超过96.951 m V;在负载电流范围0至2 A时,系统的最高转换效率可达90.92%。更多还原

【Abstract】 As a critical power supply component for various electronic devices,the performance of power management chips directly influences the overall performance of electronic products.This thesis proposes the design of a Buck-Boost DC-DC converter based on a four-switch architecture.The converter integrates heavy-load PWM modulation,light-load Burst Mode modulation,a four-mode operation strategy,and voltage mode control.The primary objective is to optimize the single-cycle operation mode to minimize the static operating current under light-load conditions,thereby enhancing the conversion efficiency across the entire load range.The research content focuses on three key aspects:Firstly,the internal bandgap reference circuit has been enhanced.By configuring the number of repetitive units generatingΔV_BEin the reference voltage generation module,the output reference voltage can be flexibly adjusted.Adjusting the input ratio of I_PTATand I_CTATensures that the temperature coefficient of the reference voltage approaches zero,achieving low temperature drift in the output reference voltage.Simulation results indicate a temperature drift coefficient of 1.56 ppm/℃.The use of multipleΔV_BErepetitive units reduces system mismatch through statistical averaging effects,with simulation results demonstrating an accuracy of 99.5%.Additionally,a segmented temperature compensation circuit has been implemented to further enhance temperature stability.Secondly,improvements have been made to the internal low-dropout linear regulator（LDO）circuit.A two-stage operational amplifier was designed to significantly increase the LDO loop gain.A transient enhancement circuit effectively suppresses the impact of input voltage fluctuations and load transients on the output voltage.A programmable trimming resistor network(R_trim)addresses deviations in the output voltage under different process corners,with a trimming step size of 0.77 m V,thereby improving output voltage precision.Furthermore,a loop compensation network ensures enhanced loop stability for the LDO circuit.Finally,circuits for generating low-threshold comparison voltages,detecting peak inductor currents,and monitoring reverse inductor currents were developed for light-load operation.In Burst Mode modulation,the switching frequency is reduced,minimizing the number of switching cycles.Simultaneously,certain chip modules are placed in sleep mode to lower static current consumption.The adoption of low-threshold comparison voltages and fewer detection cycles further reduces power dissipation,resulting in a significant improvement in conversion efficiency under light-load conditions,with a maximum enhancement of up to 2.8 times.Based on the aforementioned research,the 0.18μm BCD process was employed,and Cadence Virtuoso software was utilized to conduct precise simulations of each sub-module and the overall circuit.Following the completion of layout design and tape-out,the chip underwent testing to validate its performance metrics.The test results indicate that the system operates within an input voltage range of 2.7 V to 40 V,maintaining a stable output voltage of 5 V.Under heavy load conditions,the output voltage ripple in all operating modes remains below 144.3 m V;under light load conditions,the output voltage ripple in all operating modes remains below 96.951 m V.When the load current varies between 0 and 2 A,the system achieves a maximum conversion efficiency of 90.92%.更多还原