【作者】 王晨；

【导师】 吴振宇；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2024， 硕士

【摘要】 功率垂直双扩散场效应晶体管（Vertical Double-Diffused MOSFET,VDMOS）可以为各类电机提供电源驱动且具有耐压值高、易实现短沟道和负温度系数等众多优点,被广泛应用于宇航电子系统中的电源电路。而大量研究表明,器件内部存在的寄生双极晶体管（Bipolar Junction Transistor,BJT）和栅氧化层,在空间辐射环境中极易引发单粒子烧毁（Single Event Burnout,SEB）和单粒子栅穿（Single Event Gate Rapture,SEGR）,二者均属于不可恢复的硬错误,会对器件造成灾难性的硬损伤,严重制约了其在航天领域的应用。因此,有必要对功率VDMOS器件抗单粒子效应加固技术进行研究且需要权衡对器件静态特性的损失。本文的研究工作和成果如下:（1）研究了功率VDMOS器件单粒子烧毁失效机理并从粒子特性和外加偏置电压两方面得到了SEB敏感性。通过对比漏压70 V和40 V下粒子入射前后寄生BJT发射结附近的电势、内部电场、碰撞电离率、电流密度和晶格温度分布,得到SEB失效机理,即外延层/衬底界面的碰撞电离过程和寄生BJT的正向放大形成正反馈,使得器件内部的晶格温度持续升高,达到硅材料的熔点,发生烧毁。（2）比较了N+源区、P体区、P+区、外延层、缓冲层和载流子寿命控制这6种加固手段下器件SEB阈值电压(SEB Threshold Voltage,V_th,SEB)的提升效果及牺牲的静态特性。结果表明,降低N+源区掺杂浓度和结深对V_th,SEB提升很小;外延层最优掺杂浓度下,增加外延层厚度和将载流子寿命降低至1 ns虽可以提升器件抗SEB能力但会导致静态特性的严重退化,因此上述三种加固手段需谨慎考虑。而适当增大P体区掺杂浓度和结深、P+区的面积会使V_th,SEB有不同程度的提升且静态特性牺牲不大,因此可以适当采取。此外,优化靠近衬底的部分外延层掺杂分布,V_th,SEB可以提升至13.2%BV,同时R_on,sp降低13.7%;在外延层和衬底之间添加50μm厚掺杂浓度为3×10¹⁵ cm^-3缓冲层可以使器件在击穿电压下对SEB免疫,且仅增加7.3%的R_on,sp。（3）研究了功率VDMOS器件单粒子栅穿失效机理并从粒子特性和外加偏置电压两方面开展了SEGR敏感性研究。通过分析漏压为130 V时粒子入射前后Si-SiO₂界面堆积的空穴浓度、电势和栅氧化层上的电场分布,得到SEGR失效机理,即粒子入射电离产生的空穴除了被源电极收集外,其余的会堆积在Si-SiO₂界面,伴随着空穴电流通路的形成,漏压会逐渐耦合到界面处,从而在栅氧化层上形成瞬态电场,与静态电场叠加,使得栅氧化层上的电场达到10 MV/cm,器件发生单粒子栅穿。（4）比较了采用栅氧化层、颈区宽度、高K栅介质、外延层、缓冲层、载流子寿命和颈区介质这7种加固手段下器件SEGR阈值电压的提升效果及牺牲的静态特性。结果表明,降低外延层掺杂浓度对器件抗SEGR能力提升很小;增加栅氧化层厚度、增加外延层厚度、将载流子寿命降低到1 ps和减小颈区宽度均可以提升器件抗SEGR能力,但会导致静态特性严重退化,因此上述四种加固手段需谨慎考虑。而分别用Si₃N₄和HfO₂高K栅介质替换二氧化硅和添加25μm厚掺杂浓度为4×10¹⁵ cm^-3缓冲层结构可以在静态参数波动5%的范围内大幅提升器件的抗SEGR能力。此外,提出了缓冲层和局部载流子寿命控制联合的多加固手段,相比于仅采用缓冲层和仅采用载流子寿命控制,其能更好地在器件静态参数波动5%的范围内大幅提升SEGR阈值电压,从而为VDMOS器件的抗辐射优化设计提供理论参考。更多还原

【Abstract】 Power VDMOS can provide power drive for various motors in electronic systems,and are widely used in power circuits of aerospace electronic systems because of its many advantages such as high breakdown voltage,easy formation of short channels,and negative temperature coefficient.However,many studies have shown that due to the parasitic BJT and gate oxide layer,single event burnout and single event gate rapture failures are prone to easily occur in radiation environment,both of which can cause catastrophic hard damage and limit its application in aerospace severely.Therefore,it is necessary to research the hardening techniques for single event effects in power VDMOS devices and weigh the loss of ststic characteristics.The research work and achievements of this article are as follows:（1）The failure mechanism of single event burnout of power VDMOS devices and the SEB sensitivity which includes the incident particle and applied bias voltage are investigated.By comparing the distributions of potential near the parasitic BJT emitter junction,internal electric field,impact ionization rate,current density and lattice temperature before and after particle incidence under the drain voltages of 70 V and 40 V,the SEB failure mechanism is obtained.That is,the impact ionization process at the epitaxial/substrate interface and the forward amplification of the parasitic BJT form a positive feedback,causing the lattice temperature inside the device continued to rise,and reaching the melting point of silicon material,thus burnout occurred.（2）Comparing the improvement of the SEB threshold voltage and the sacrificed static characteristics of the device under six hardening techniques:N+source,P body region,P+region,epitaxial layer,buffer layer,and carrier lifetime control.The simulation results indicate that reducing the peak doping concentration and junction depth of N+source have little improvement on V_th,SEB.Optimizing the doping concentration of epitaxial layer,increasing the thickness of epitaxial layer,and reducing the carrier lifetime to 1 ns could improve the SEB tolerance but they also lead to severe static degradation.Therefore,these three hardening methods are usually not adopted.On the other hand,appropriately increasing the doping concentration and junction depth of P body and the area of P+region enhance V_th,SEB to varying degrees with minimal sacrifice to static characteristics,making them suitable for adoption.Additionally,optimizing the doping distribution in the epitaxial layer near the substrate could increase V_th,SEB to 13.2%of the breakdown voltage while reducing R_on,sp by 13.7%.Moreover,introducing a 50μm thick buffer layer structure with a doping concentration of 3×10¹⁵ cm^-3 between the epitaxial layer and the substrate makes the device immune to SEB at the breakdown voltage while only increasing R_on,sp by 7.3%.（3）The failure mechanism of single event gate rupture（SEGR）in power VDMOS devices is studied,and the SEGR sensitivity is also investigated from the incident particle characteristics and applied bias voltage.By analyzing the hole concentration accumulation at the Si-SiO₂ interface,the internal potential,and electric field distribution on the gate oxide layer after particle incidence at a drain voltage of 130 V,the SEGR failure mechanism is obtained.Specifically,the holes generated by particle incidence ionization accumulates at the Si-SiO₂ interface.With the formation of current path,the drain voltage gradually coupled to the interface and neck region,creating a transient electric field on the gate oxide layer.When the transient electric field superimposes with the static electric field,the electric field on the gate oxide layer reaches 10 MV/cm,leading to single event gate rupture of the device.（4）Comparing the enhancement effects on SEGR threshold voltage and sacrificed electrical characteristics of seven hardening methods,including gate oxide,neck region width,high-K gate dielectrics,epitaxial,buffer,carrier lifetime,and neck dielectrics.The results indicate that reducing the doping concentration of epitaxial has minimal impact on the SEGR tolerance.Increasing the thickness of gate oxide,epitaxial layer,and reducing the carrier lifetime to 1 ps,and narrowing the neck region width,could all enhance the SEGR tolerance,but lead to significant degradation of static characteristics.However,replacing silicon dioxide with high-K gate dielectrics such as Si₃N₄ and HfO₂,and introducing a 25μm thick buffer layer structure with a doping concentration of 4×10¹⁵ cm^-3,could significantly improve the SEGR resistance of the device within a 5%fluctuation range of the static parameters.Additionally,a combined method of buffer layer and local carrier lifetime control is proposed.Compared with the method that only uses buffer layer or only uses carrier lifetime control,it can greatly increase the SEGR threshold voltage of the device within the range of 5%fluctuation of static parameters of the device,thus providing a theoretical reference for the optimization design of anti-radiation of VDMOS devices.更多还原