【作者】 黄蕾；

【导师】 来逢昌；

【作者基本信息】 哈尔滨工业大学 ， 电子科学与技术， 2023， 硕士

【摘要】 随着电子产品的爆发式增长,如今的SoC芯片不仅要拥有良好的性能,还要拥有较低的功耗。后端设计作为SoC芯片设计过程中的关键一环,其设计过程对芯片的最终功耗具有很大的影响。SoC后端通用开发平台可以准确、高效地完成SoC传统后端设计过程,如果可在此平台的基础上,增加低功耗组件的设计,在不影响芯片版图文件生成的同时考虑到芯片的功耗情况,将具有重大的意义。本文将多种低功耗技术与SoC后端设计流程相结合,实现低功耗组件的设计。低功耗组件可以分为设计和验证两大部分,设计部分包括低功耗逻辑综合组件和低功耗物理设计组件。对Design Compiler支持的功耗优化技术进行分析,设计低功耗逻辑综合组件,实现硬件描述语言到特定逻辑库的优化门级网表的转换,且在此过程中可以应用时钟门控、多电源电压技术、电源门控、多阈值电压优化等多种可以降低功耗的技术。根据传统物理设计及低功耗物理设计过程,设计适配于低功耗逻辑综合组件的低功耗物理设计组件,实现综合优化后的门级网表到版图文件的转换。验证部分包括低功耗形式验证组件和低功耗静态时序分析组件。对Formality形式验证流程进行细分,设计低功耗形式验证组件,在读入设计的同时可以进行UPF文件的读入,实现不同设计的等价性验证过程。低功耗静态时序分析组件利用PrimeTime进行单一电压域或多电压域设计的路径划分、延时计算与时序检查的过程,并借助PrimeTime-PX执行功耗分析,直观查看设计的功耗情况。最后,应用添加了低功耗组件的SoC后端通用开发平台,在设计人员少量介入下,实现各组件的功能,从而完成一款基于Cortex-M3的数字SoC芯片的低功耗后端全流程设计,并将此时的功耗与使用原始SoC后端通用开发平台完成后端设计后的功耗进行对比,功耗降低了18%左右。更多还原

【Abstract】 With the explosive growth of electronic products,today’s SoC chips need not only good performance,but also low power consumption.As a key part of SoC chip design,back-end design has great influence on the final power consumption of the chip.The general development platform of SoC back-end can complete the traditional back-end design process of SoC accurately and efficiently.If the design of low-power components can be added on the basis of this platform,it will be of great significance to consider the power consumption of chips while not affecting the generation of chip layout files.In this paper,a variety of low-power technologies are combined with the SoC back-end design process to realize the design of low-power components.Low power components can be divided into two parts: design and verification.The design part includes low power logic synthesis component and low power physical design component.Power optimization technologies supported by the Design Compiler were analyzed,and low-power logic synthesis components were designed to realize the conversion of hardware description language to optimized gate netlists of specific logic libraries.In this process,various technologies that could reduce power consumption,such as clock gating,multi-power supply voltage technology,power supply gating,and multi-threshold voltage optimization,could be applied.According to the traditional physical design and low power physical design process,low power physical design components suitable for low power logic synthesis components are designed to realize the conversion of gate level netlist to layout file after comprehensive optimization.The verification part includes low power formal verification component and low power static timing analysis component.Formality validation components of low power are designed after subdividing the validation process of Formality.Besides reading into the design,UPF files can be read into formality validation process of different designs,so as to realize the equivalence verification process of different designs.The low-power static timing analysis component uses PrimeTime to carry out the process of path division,delay calculation and timing inspection for the design of single voltage domain or multi-voltage domain,and performs power analysis with Primetime-PX to visually check the power consumption of the design.Finally,the general development platform of SoC back-end with low power components is applied,and the functions of each component are realized with a small amount of intervention of designers,thus completing the whole process design of a low power back-end based on Cortex-M3 digital SoC chip.The power consumption at this time is compared with that after the back-end design is completed using the original general SoC back-end development platform,and the power consumption is reduced by about 18%.更多还原