【作者】 张永强；

【导师】 明鑫；

【作者基本信息】 电子科技大学 ， 电子信息（专业学位）， 2024， 硕士

【摘要】 基于GaN宽禁带半导体优良的材料特性,GaN HEMT具有同耐压级别下更小的栅极电荷Q_G和输出电容Coss,这使其在高频高压的应用场景下具备良好的应用优势,可有效减小电源系统的无源器件面积,提高电源系统的功率密度和效率。然而GaN器件的使用给驱动芯片带来了崭新的设计挑战,尤其是在高压半桥系统当中。600 V增强型器件5～6 V的栅压窗口限制了芯片的供电范围,同时自举向高侧浮动电源轨供电会带来充电饱和度或过充的问题;体二极管的缺乏一方面提高了GaN功率管的开关速度,另一方面下管反向导通续流时造成更大的死区负压,死区时间过长时会带来更大的导通损耗,死区时间过短时又会有穿通和硬开关的风险;GaN器件过快的开关速度会带来巨大的d V/dt和di/dt问题,在600 V半桥系统当中,正向d V/dt的影响尤为显著,其一方面会直接耦合到下管栅极和高侧驱动电路当中,另一方面会通过寄生电感滋生高频EMI干扰系统正常工作。针对GaN器件栅极电压敏感性和半桥系统浮动电压域跳变带来的挑战,本文设计了一套涉及五个电源轨和三个参照地的芯片二次供电方案,通过双侧片上集成LDO,实现9～20 V宽供电范围下输出5.2 V的有效钳位。同时低侧通过分地设计和集成数字电源轨LDO的方式确保所有电压域下电路正常工作。针对GaN半桥系统死区时间过长或过短带来的损耗和穿通问题,本文设计了一套外部电阻编程死区时间调制方案,根据系统VIN、I_O和CSW等应用参数计算最优死区时间,在给定较小固有死区时间的情况下,通过外部电阻编程可实现20ns～150 ns的死区时间插入。针对GaN开启过程过快造成的d V/dt和di/dt问题,本文在高侧利用600 V LDMOS检测d V/dt,提出了一套三段式N型上拉驱动方案,依靠较小的R_G实现50 V/ns的正向d V/dt控制,节省了上管的开关损耗和开启延时;同时在低侧本文也提出一套电荷泵辅助N管上拉的驱动方案,能够以较小的驱动管面积实现了对GaN管栅极5.2 V的饱和上拉能力。最后本文基于0.8μm 600 V BCD工艺,将本文提出的技术方案在芯片级进行整仿验证,并给出流片版图设计,版图尺寸2.1 mm×3.1 mm。更多还原

【Abstract】 Based on the excellent material properties of GaN wide bandgap semiconductors,GaN HEMT has smaller gate charge QG and output capacitance Coss at the same voltage level,which makes it have good application advantages in high-frequency and highvoltage application scenarios.It can effectively reduce the passive device area of power systems,improve the power density and efficiency of power systems.However,the use of GaN devices has brought new design challenges to driver chips,especially in high-voltage half bridge systems.The gate voltage window of 5～6 V for 600 V enhanced devices limits the power supply range of the chip,and bootstrap power supply to the high side floating power rail can cause charging saturation or overcharging issues;The lack of body diodes not only improves the switching speed of GaN power transistors,but also causes greater dead zone negative pressure when the bottom transistor conducts freewheeling in reverse.If the dead zone time is too long,it will bring greater conduction loss.If the dead zone time is too short,there is a risk of breakdown and hard switching;The excessive switching speed of GaN devices can cause significant d V/dt and di/dt issues.In a 600 V half bridge system,the impact of forward d V/dt is particularly significant.On the one hand,it directly couples to the lower gate and high side drive circuit,and on the other hand,it can breed high-frequency EMI interference through parasitic inductance to ensure the normal operation of the system.In response to the challenges posed by gate voltage sensitivity of GaN devices and floating voltage domain jumps in half bridge systems,this thesis proposes a chip secondary power supply scheme involving five power rails and three reference grounds.By integrating LDO on both sides of the chip,an effective clamping of 5.2 V output is achieved over a wide power supply range of 9～20 V.At the same time,the low side ensures the normal operation of the circuit in all voltage domains through ground separation design and integration of digital power rail LDO.In response to the loss and breakdown problems caused by the long or short dead time of the GaN half bridge system,this thesis designs an external resistance programming dead time modulation scheme.The optimal dead time is calculated based on the application parameters of the system VIN,IO,and CSW.Given a smaller inherent dead time,a dead time insertion of 20 ns to 150 ns can be achieved through external resistance programming.In response to the d V/dt and di/dt issues caused by the rapid opening process of GaN,this thesis proposes a three-stage N-type pull-up drive scheme using a 600 V LDMOS to detect d V/dt on the high side,relying on a smaller RG to achieve forward d V/dt control of 50 V/ns,saving switching losses and opening delay of the upper transistor;At the same time,this article also proposes a charge pump assisted N-transistor pull-up driving scheme on the low side,which can achieve a saturation pull-up capability of 5.2 V on the GaN transistor gate with a smaller driving transistor area.Finally,this article is based on 0.8 μ The technology proposed in this article will be simulated and validated at the chip level using the m600 V BCD process,and a chip layout design will be provided with a layout size of 2.1 mm x 3.1 mm.更多还原