【作者】 冯玮；

【导师】 彭析竹；

【作者基本信息】 电子科技大学 ， 电子信息（专业学位）， 2024， 硕士

【摘要】 集成有传感器处理接口的模拟前端电路(AFE),是物联网时代信号链处理系统中极其关键的部分。自然界中的物理信息被传感器采集之后,只有经过模拟前端电路,才能在数字域进行处理,因此通常将模拟前端电路称为模拟与数字世界的“桥梁”。在AFE电路中起到核心作用的是模数转换器(ADC)模块,负责将连续的模拟信号量化成离散的数字信号,ADC模块有其固定的量化范围与精度,但采集端所处的环境通常比较复杂,信号强度变化较大,同时还会包含一些环境噪声,这要求在采集端与ADC之间增加运算放大器模块,主要起提供动态增益、抑制共模干扰、稳定信号输出幅度的作用,可变增益放大器(Variable gain amplifier,VGA)也就成为了模拟前端的核心模块之一。可变增益放大器属于仪表放大器的一种,根据控制信号的不同可以分为电压控制的连续增益变化的模拟型VGA与数字控制的增益步进可调的数字型VGA,其中数字型VGA在电路设计上更为简单,增益精度更高,因此被广泛应用。通常又将数字型VGA称为可编程增益放大器(Programmable gain amplifier,PGA),本文设计的即为一款应用于高精度SAR ADC的PGA模块。本文首先介绍了可编程增益放大器的基本结构,对几种架构的优缺点进行分析,同时给出了PGA设计中需要关注的重要指标。接着对PGA中内部开环运放逐级进行设计,利用开环运放的高增益提高输出线性度及增益精度,其中输出级采用Class AB结构增大输出摆幅,针对输出级的跨导线性环偏置设计了辅助运放来稳定静态输出电流,进一步提高运放线性度;然后,采用具有调零电阻的嵌套式米勒补偿来解决多级运放的稳定性问题,考虑到三级全差分运放的复杂性,设计了双共模反馈来约束静态工作点。此外,在外部反馈电阻上并联电容以使PGA兼具低通滤波的性能,反馈电阻与反馈电容在不同的增益档位下以同比例扩大与缩小,最终实现带宽的相对稳定。最后,本文对以上设计的电路进行了仿真验证,确保电路能够满足指标要求。仿真结果表明,电路在3.3V电源下可提供1/2/4/8倍四种增益档位,滤波器带宽稳定在100KHz附近,THD可达-121.86d B,等效输入噪声为15.25μV。电路基于180 nm CMOS工艺设计,并进行了版图绘制与后仿。更多还原

【Abstract】 The analog front-end circuit(AFE)integrated with sensor processing interfaces is an extremely critical part of the signal chain processing system in the era of the Internet of Things.After physical information in nature is collected by sensors,it can only be processed in the digital domain through analog front-end circuits.Therefore,analog frontend circuits are commonly referred to as the "bridge" between the analog and digital worlds.The analog-to-digital converter(ADC)module plays a core role in the AFE circuit,which is responsible for quantifying continuous analog signals into discrete digital signals.The ADC module has a fixed quantization range and accuracy,but the environment at the acquisition end is usually complex,with significant changes in signal strength and some environmental noise.This requires the addition of an operational amplifier module between the acquisition end and the ADC,mainly to provide dynamic gain,suppress common mode interference,and stabilize signal output amplitude.The Variable gain amplifier(VGA)has become one of the core modules in the analog front-end.Variable gain amplifier belongs to a type of instrument amplifier,which can be divided into analog VGA with continuous gain change controlled by voltage and digital VGA with stepwise adjustable gain controlled by digital according to different control signals.Among them,digital VGA is more simple in circuit design and has higher gain accuracy,so it is widely used.Digital VGA is commonly referred to as programmable gain amplifier(PGA),and this thesis designs a PGA module for high-precision SAR ADCs.Firstly,the basic structure of programmable gain amplifiers is introduced,and the advantages and disadvantages of several architectures are analyzed.At the same time,important indicators that need attention in PGA design are given.Next,the internal openloop operational amplifier in PGA is designed step by step,utilizing the high gain of the open-loop operational amplifier to improve output linearity and gain accuracy.The output stage adopts a Class AB structure to increase output swing,and an auxiliary operational amplifier is designed for the cross wire loop bias of the output stage to stabilize the static output current and further improve the linearity of the operational amplifier;Then,a nested Miller compensation with zero resistance is used to solve the stability problem of the multi-level operational amplifier.Considering the complexity of the three-level fully differential operational amplifier,a dual common mode feedback is designed to constrain the static operating point.In addition,a capacitor is parallel connected to the external feedback resistor to enable PGA to have low-pass filtering performance.The feedback resistor and feedback capacitor expand and shrink in the same proportion at different gain levels,ultimately achieving relative bandwidth stability.Finally,simulation verification was conducted on the circuit designed above to ensure that it meets the requirements of the specifications.The simulation results show that the circuit can provide four gain levels of 1,2,4and 8 times under 3.3V power supply.The filter bandwidth is stable around 100 KHz,with a THD of-121.86 d B and an equivalent input noise of 15.25 μV.The circuit is designed based on the 180 nm CMOS process and layout drawing was performed and post-circuit simulation was done.更多还原