【作者】 罗丽；

【导师】 巫江；

【作者基本信息】 电子科技大学 ， 光学工程， 2024， 硕士

【摘要】 目前,二维材料因其具备优异的光电特性和单原子或单分子的结构特征,使其广泛应用于光电检测和成像领域中。由于二维材料探测器输出信号微弱,使得以二维材料探测器阵列为核心的成像系统在实际应用中面临诸多挑战,如成像精度、读出电路速度等。因此,本文从读出电路的量化速度、功耗、面积等角度综合考虑,设计一种适合其读出的12位列级模数转换器(ADC),本文工作如下:(1)针对列并行ADC进行研究与分析,传统单斜坡ADC(SS ADC)的面积小、结构简单;逐次逼近型ADC(SAR ADC)的量化速度快、功耗低。通过建模仿真发现,随着量化位数N增加,SS ADC量化速度降低,而SAR ADC电容阵列面积变大。为减小电路尺寸和提升量化速度,本文提出12位列并行单端SAR/SS混合架构的ADC。(2)在MATLAB中对SAR/SS混合架构ADC进行行为级仿真,经过建模和结果分析,所提出的架构模型在理论上可行。12位SAR/SS混合架构ADC由电容型数模转换器(DAC)、SAR/SS逻辑电路、斜坡发生器、比较器、计数器等电路模块构成。在该结构中,SAR ADC与SS ADC复用一个比较器和电容阵列模块以进一步降低面积和功耗。采用高低双时钟10M/20M控制量化过程,加快量化速度。其中,粗量化阶段由7 bit SAR ADC完成、细量化阶段由5 bit SS ADC完成。因此,与传统12位SAR ADC相比,电容阵列版图面积降低了68.75%;而与传统的12位SS ADC相比,量化速度提高了98%。同时,引入相关双采样技术降低噪声和失调的影响、提升电路稳定性。(3)在55nm CMOS工艺下,对精度为12 bit、采样率为285 k S/s的列并行单端SAR/SS混合架构ADC进行前仿真。结果表明在引入1位冗余位后,SAR/SS ADC的有效位数(ENOB)从9.685 bit提升到11.47 bit,信噪比(SNR)也从60.07d B提升到70.82 d B,微分非线性误差(DNL)和积分非线性误差(INL)分别为+0.63/-0.48LSB和+0.29/0.98LSB。该ADC完成一次量化的时间为3.5 us、功耗为18u W,其中斜坡发生器功耗0.268m W,能够满足分辨率为1024H×960V、帧频60fps的探测器阵列读出。最后,基于单个二维材料偏振探测器搭建了偏振识别显示系统,为列级SAR/SS ADC应用于阵列型偏振探测器以实现偏振成像提供理论基础和实践经验。更多还原

【Abstract】 Currently,two-dimensional materials have garnered considerable attention in the field of photoelectric detection and imaging owing to the outstanding photoelectric properties and structural characteristics with single atoms or molecules.However,due to the weak output signal of 2D material detectors,the imaging systems based on 2D materials detector arrays faces numerous challenges in practical scenarios,such as imaging accuracy and readout circuit speed.Therefore,the work design a 12-bit columnlevel analog-to-digital converter(ADC)tailored for readout circuits,taking into account factors such as speed,power consumption,and area.The specific work are as follows:(1)A study and analysis of column-level ADC are conducted: Traditional singleslope ADC(SS ADC)offers compact size and simple structure,and SuccessiveApproximation ADC(SAR ADC)provides fast quantization speed and low power consumption.After modeling and simulation,it is found that the quantization speed of SS ADC decreases,while the area of SAR ADC capacitor arrays increases with the quantization bit N increases.To address this,a 12-bit column parallel single-ended SAR/SS hybrid architecture ADC is proposed to reduce circuit size and enhance quantization speed.(2)Behavior-level simulations of SAR/SS hybrid architecture ADC are conducted in MATLAB,demonstrating the feasibility of proposed architecture model in theory.The12-bit SAR/SS hybrid architecture ADC consists of the capacitive digital-to-analog converters(DAC),SAR/SS logic circuits,ramp generators,comparators,counters,and other circuit modules.The SAR ADC and SS ADC share a comparator and capacitor array module to further reduce area and power consumption.Leveraging high-low dual-clock10M/20 M control for quantization,the ADC achieves accelerated quantization speed.The coarse quantization stage is completed by a 7-bit SAR ADC,while the fine quantization stage employs a 5-bit SS ADC.As a result,the layout area of the capacitor array is reduced by 68.75% compared to traditional 12-bit SAR ADC,and the quantization speed is increased by 98% compared to traditional 12-bit SS ADC.Additionally,Correlated Double-Sampling technology is introduced to minimize noise,imbalance effects and enhance circuit stability.(3)Pre-simulation of a column-level single-ended SAR/SS hybrid architecture ADC with 12-bit accuracy and a sampling rate of 285 k S/s is conducted by 55 nm CMOS process.The results indicate that after introducing one redundant bit,the Effective Number of Bits(ENOB)of the SAR/SS ADC increased from 9.685 bits to 11.47 bits,and the Signal-to-Noise Ratio(SNR)improved from 60.07 d B to 70.82 d B.The Differential Nonlinearity error(DNL)and Integral Nonlinearity error(INL)were +0.63/-0.48 LSB and+0.29/-0.98 LSB,respectively.The ADC completes a quantization in 3.5 μs with a power consumption of 18 u W and the ramp generator consumption is 0.268 m W,meeting the requirements for detector array readouts with a resolution of 1024H×960V and a frame rate of 60 fps.Finally,a polarization recognition display system based on a single 2D material polarization detector is established,providing theoretical foundations and practical experience into applying column-level SAR/SS ADC to array polarization detectors for polarization imaging realization.更多还原