【作者】 张莹；

【导师】 刘兴辉；

【作者基本信息】 辽宁大学 ， 微电子学与固体电子学， 2024， 硕士

【摘要】 在高速SerDes(Serializer/Deserializer,串行器/解串器)系统中,随着数据传输速率越来越高,信道中的高频损耗、反射及噪声等非理想特性对数据产生的衰减越来越严重,致使数据产生严重的失真,从而降低系统性能。为了改善接收端的信号传输质量,各类均衡技术被广泛应用于高速SerDes系统中,而连续时间线性均衡器(Continuous Time Linear Equalizer,CTLE)作为SerDes系统接收端的重要模块,其对高频衰减的补偿能力影响着整个SerDes系统的性能,因此研究并改进连续时间线性均衡器的电路结构对高速通信系统的发展具有重要意义。本文设计了一款应用于高速SerDes接收端的自适应连续时间线性均衡器,此设计主要包括CTLE均衡模块、DAC电流源模块和自适应算法模块。为解决传统CTLE高频补偿能力欠缺和无法适应不同信道衰减的问题,本文在传统CTLE的基础上,级联低频均衡器,该均衡器采用双路源级负反馈电阻电容差分结构,对低频信号实现补偿的同时,通过源级负反馈电阻和电容引入了一对零极点,可实现对高频信号的二次补偿;同时,将基于码型检测的符号化最小均方根(Sign-Sign Least Mean Squares,SS-LMS)算法应用于CTLE均衡技术中,使其能根据信道环境的变化产生动态的均衡系数,来调节零极点位置,进而产生不同的增益补偿,达到适应不同信道衰减的目的。本文基于TSMC 28nm CMOS工艺对所设计电路的版图进行绘制,并通过后仿真验证。后仿真结果显示,12.5Gb/s的数据经过背板信道后,在奈奎斯特频率处产生严重衰减,经过自适应CTLE均衡后,PVT工艺角下,目标频率处的增益补偿范围在14.75dB-21.79dB之间,均衡后的眼图水平张开度在0.81UI-0.92UI之间,抖动小于0.2UI,同时,通过例举-13.42dB、-16.32dB、-20.90dB三种不同信道衰减幅度,所设计的自适应CTLE均能够对传输数据进行有效均衡,改善信号传输质量。更多还原

【Abstract】 In high-speed SerDes(Serializer/Deserializer)systems,as the data transmission rate increases,non-ideal features such as high frequency loss,reflection,and noise in the channel attenuate data more and more seriously,resulting in serious data distortion and system performance deterioration.In order to improve the signal transmission quality at the receiving end,various equalization technologies are widely used in high-speed SerDes systems,and Continuous Time Linear Equalizer(CTLE)is an important module at the receiving end of SerDes systems.Its ability to compensate high frequency attenuation affects the performance of the whole SerDes system,so it is of great significance to study and improve the circuit structure of continuous time linear equalizer for the development of high-speed communication system.In this paper,an adaptive continuous time linear equalizer is designed for high-speed SerDes receivers,which mainly includes CTLE balancing module,DAC current source module and adaptive algorithm module.In order to solve the problem that traditional CTLE lacks high-frequency compensation capability and can not adapt to different channel attenuation,on the basis of traditional CTLE,the CTLE designed in this paper cascades low-frequency equalizers,the equalizer adopts a dual source negative feedback resistor capacitor differential structure,which compensates for low-frequency signals while introducing a pair of zero poles through source negative feedback resistors and capacitors,enabling secondary compensation for high-frequency signals;At the same time,the Sign-Sign Least Mean Squares(SS-LMS)algorithm based on code pattern detection is applied to CTLE equalization technology,so that it can generate dynamic equalization coefficient according to the change of channel environment,adjust the zero pole position,and then produce different gain compensation.To achieve the purpose of adapting to different channel attenuation.The layout of the designed circuit is drawn based on TSMC 28 nm CMOS technology and post simulation verification is passed.The post simulation results show that the 12.5Gb/s data undergoes severe attenuation at the Nyquist frequency after passing through the backplane channel.After adaptive CTLE equalization,the gain compensation range at the target frequency under the PVT process corner is between 14.75 dB-21.79 dB,and the horizontal eye opening after equalization is between 0.81UI-0.92 UI,with jitter less than 0.2UI.Meanwhile,by citing three different channel attenuation amplitudes-13.42 dB,-16.32 dB,and-20.90 dB,the designed adaptive CTLE can effectively balance the transmitted data and improve signal transmission quality.更多还原