【作者】 陈宇；

【导师】 吴金； 刘桂芝；

【作者基本信息】 东南大学 ， 集成电路工程（专业学位）， 2022， 硕士

【摘要】 模数转换器(Analog to Digital Converter,ADC)在模拟与数字之间起到桥梁作用,广泛应用于各种电子产品中。随着5G时代的到来,对低功耗模数转换器的需求日益迫切,同时对其精度的要求越来越高。在各种ADC结构中,电容式SAR ADC能够较好的满足低功耗、中高精度的应用要求,因此受到集成电路产业的广泛重视。受制于工艺漂移,电容失配将带来SAR ADC精度的严重退化,限制了有效位数以及线性度的提高,校准技术也因此成为提升SAR ADC精度的关键。本文设计了一款转换速率为2MS/s、分辨率为14位并具备数字校准功能的SAR ADC电路,电源电压为1.8V。此SAR ADC电路包括采样开关、DAC电容阵列、比较器、控制逻辑及校准等模块。针对电路高精度的要求,采用倍压式栅压自举开关,可以有效提升输入采样开关的精度,从而抑制系统有效位数的损失。本文采用两段式DAC电容阵列,显著节省芯片面积并降低功耗,两段式电容阵列之间采用整数桥接电容,以降低因分数电容导致的电容失配,有效改善系统线性度。针对DAC电容阵列的电容失配会严重影响系统精度的问题,设计了用于两段式电容阵列的数字校准算法,此算法对欠二进制权重失配有校准作用可有效提升SAR ADC转换精度。为了满足高精度SAR ADC的量化需求,采用预放大锁存比较器结构,以实现较高的增益和响应速度,此外还添加了IOS和OOS结构对比较器的失调电压进行校准。本文基于TSMC 0.18μm CMOS工艺,完成电路、版图设计、仿真验证与测试。测试结果表明:设计的SAR ADC具备采样保持、逐次逼近、校准等基本功能,在采样率为2MS/s、输入信号为0.984375MHz频率下,系统平均功耗为988.6μW。校准前,系统有效位数为9.95bit,信噪失真比为61.6d B;校准后,信噪失真比为77.3d B,有效位数提高到12.5bit。更多还原

【Abstract】 Analog to digital converter(ADC),as a bridge connecting analog signals and digital signals,is widely used in various electronic products.With the advent of 5g era,the demand for low-power analog-to-digital converter is becoming more urgent,and the demand for its accuracy is becoming higher and higher.Among various ADC structures,capacitive SAR ADC can better meet the application requirements of low power consumption,medium and high precision,so it has been widely valued by the integrated circuit industry.Subject to process drift,capacitance mismatch will lead to serious degradation of SAR ADC accuracy,limiting the improvement of effective bits and linearity.Therefore,calibration technology has become the key to improve SAR ADC accuracy.This paper designs a SAR ADC circuit with conversion rate of 2ms / s,resolution of 14 bits and digital calibration function.The power supply voltage is 1.8V.The SAR ADC circuit includes sampling switch,DAC capacitor array,comparator,control logic and calibration modules.According to the requirements of high precision of the circuit,the voltage doubling grid voltage bootstrap switch can effectively improve the accuracy of the input sampling switch,so as to suppress the loss of effective digits of the system.In this paper,two-stage DAC capacitor array is used to significantly save chip area and reduce power consumption.Integer bridging capacitor is used between the two-stage capacitor array to reduce the capacitor mismatch caused by fractional capacitance and effectively improve the system linearity.Aiming at the problem that the capacitance mismatch of DAC capacitor array will seriously affect the system accuracy,a digital calibration algorithm for two-stage capacitor array is designed.This algorithm can effectively improve the SAR ADC conversion accuracy for the calibration of under binary weight mismatch.In order to meet the quantization requirements of high-precision SAR ADC,a dynamic comparator structure of pre amplification and latch is adopted to achieve high gain and response speed.In addition,IOS and OOS structures are added to calibrate the offset voltage of the comparator.This paper is based on TSMC 0.18μm CMOS process,complete circuit,layout design,simulation verification and test.The post simulation results show that the designed SAR ADC has the basic functions of sample and hold,successive approximation and calibration.Under the sampling rate of 2MS/s and the input signal frequency of 0.984375 MHz,the average power consumption of the system is988.6 μW.Before calibration,the effective bit of the system is 9.95 bit and the signal-to-noise distortion ratio is 61.6d B;After calibration,the signal-to-noise distortion ratio is 77.3d B and the effective bits are 12.5bit.更多还原