【作者】 高峰；

【导师】 舒斌； 邱敏；

【作者基本信息】 西安电子科技大学 ， 工程硕士（专业学位）， 2022， 硕士

【摘要】 在过去几年的时间里,人工智能算力已经提升近万倍,面对市场对于产品需求的快速变化,如何平衡短周期与高性能成为了人工智能芯片领域竞争的关键。在整个芯片开发的项目过程中,有60%以上开发总时间消耗在芯片验证环节,且这一比重还在上涨,因此提高验证效率成为包括人工智能芯片在内的整个芯片行业业界亟待解决的核心关键问题。本文通过对目前业界广泛应用的主流验证方法与验证策略进行研究,结合NPU神经网络芯片的主要功能模块及其验证需求,针对NPU中的部分模块采用UVM动态仿真、形式化验证、原形验证等多种不同的验证方法开展验证及研究工作,同时提出随机句柄复用的UVM平台随机化效率优化改进方案,并引入PSS技术以实现测试激励跨平台跨层次复用的需求。采用基于UVM验证平台的事务级动态仿真验证方法展开Multicast功能的验证工作,其测试用例通过率收敛至100%,功能覆盖率收敛至100%;并对该平台采用随机句柄复用方式进行随机耗时优化,使得随机化耗时减少为原来的10%。采用形式化验证方法展开MMIO＿CTRL＿DMA与ALU模块的验证工作,分别研究了形式化断言验证技术与数据路径验证技术,实现了259条属性检查的100%通过以及全部37种运算方式数据通路检查的100%通过,且在合理范围内均达到了100%的属性密度覆盖要求。采用Python模块化动态仿真方法展开最大池化功能的验证工作,通过测试生成组件与随机参数组件相结合的方式生成不同平台所需要的测试用例,并对其Native模型进行仿真验证,全部24种最大池化方式实现了100%的测试用例通过率;同时还引入了PSS流程并搭建对应环境及模型,用以增强测试场景的复用性及组合性功能。采用HAPS原形验证方法,通过微处理器Dhrystone标准测试得出功耗、时序、性能等的报告,在系统时钟频率为50 MHz的情况下,其Dhrystone分数为2.699DMIPS/MHz,总功耗为13.757 W,其中静态功耗占比22%,且没有时序违例出现,基本达到了项目规格文档中指定的性能指标。根据待测设计的不同层级、功能特点及验证需求选用合适的验证策略及验证方法学,并不断引入能够提升效率或提高质量的验证新技术,成为解决平衡短周期与高性能需求这一关键问题的根本方法。更多还原

【Abstract】 In the past few years,the computing power of artificial intelligence has been improved nearly ten thousand times.Facing the rapid change of market demand for products,how to balance short cycle and high performance has become the key to the competition in the field of artificial intelligence chips.In the whole process of chip development,more than 60% of the total development time is spent in the chip verification process,and this proportion is still rising.Therefore,improving the efficiency of verification has become a key issue to be urgently solved in the whole chip industry,including artificial intelligence chips.In this paper,the mainstream verification methods and verification strategies widely used in the industry are studied.Combined with the main functional modules of NPU neural network chips and their verification requirements,UVM dynamic simulation,formal verification,prototype verification and other different verification methods are used to carry out verification and research for some modules in NPU.At the same time,random handle reuse method is proposed,which is used for optimizing the randomization efficiency problem of UVM platform,and PSS technology is introduced to meet the requirement of cross-level reuse of test excitation.The transactional-level dynamic simulation verification method based on UVM verification platform was used to verify Multicast functions.The pass rate of test cases converged to100%,and the function coverage converged to 100%.The platform uses random handle reuse to optimize the stochastic time,which reduces the stochastic time to 10%.Formal verification method is used to carry out the verification of MMIO＿CTRL＿DMA and ALU modules.Formal assertion verification technology and data path verification technology are studied respectively,achieving 100% pass of 259 assertion checks and 100% pass of data path checks of all 37 types of operation modes.And the coverage of assertion density is 100%within a reasonable range.Python modular dynamic simulation method was used to verify the maximum pooling function.Test cases required by different platforms were generated through the combination of test generation components and random parameter components,and their Native models were simulated and verified.All 24 types of maximum pooling methods achieved 100% pass rate of test cases.At the same time,the PSS process is introduced and the corresponding environment and model are built to enhance the reusability and combinability of test scenarios.HAPS prototype verification method is used to obtain power consumption,timing and performance reports through Dhrystone standard testing of microprocessors.Under the condition of 50 MHz clock frequency,the Dhrystone score is2.699 DMIPS/MHz and the total power consumption is 13.757 W,of which the static power consumption accounts for 22%.There is no timing violation,and the performance index specified in the project specification document is basically achieved.According to the different levels,functional characteristics and verification requirements of the designs under test,the selection of appropriate verification strategies and methods,and the continuous introduction of new verification technologies that can improve efficiency or quality,has become the fundamental method to solve the key problem of balancing short cycle and high-performance requirements.更多还原