【作者】 王彬；

【导师】 孔谋夫；

【作者基本信息】 电子科技大学 ， 电子科学与技术， 2022， 硕士

【摘要】 第三代半导体氮化镓(GaN)因其可以实现更高的开关频率和更高效的电源,近几年迅速发展,被逐步应用于各个领域。增强型GaN器件与Si基器件相比具有更低的导通电阻,更快的开关频率,对其栅极驱动的性能提出更高的要求,因此研究增强型GaN功率器件栅极驱动芯片的意义重大。增强型GaN功率器件由于高的饱和速度特性,使其经常用于高频场合。但是在设计基于GaN的高频驱动电路的时候,需要着重解决三大问题:1)在设计采用半桥式结构的增强型GaN功率器件的栅驱动芯片时共模瞬态抗扰度(CMTI)能力不够理想,是因为在其快速开关过程中会产生很大的dv/dt;2)传输延时大以及匹配性差;3)在快速开关过程中,结点处会产生负压等问题。本文设计了一款增强型GaN功率器件的驱动芯片,对输入信号进行检测、限幅,去掉芯片外部带来的毛刺等因素的影响。设计了多条电源轨用于驱动芯片内部正常运行。针对dv/dt问题,在设计电平位移电路时,本文提出了同时采用旁路正、负反馈电路的方法进一步提高CMTI能力;针对传输延时和匹配问题,使用输入检测电路将输入信号限幅到1.8 V,使低侧信号传输通道中同样可以设计一个和高侧信号传输通道相似的电平位移电路,设计的高低两侧相似的信号传输通道提高匹配性,在芯片内尽量采用低压器件减小RC延时,同时设计了短脉冲控制的高速电平位移电路,减小传输延时的同时降低功耗。针对负压问题,在高侧通道,本文提出在避开死区时间内充电的基础上,采用负压检测电路,双重确保结点处摆脱负压,同时本文将充电管用NMOS替代PMOS,提高充电电流,防止充电不足现象;在低侧负压发生时,本文提出采用正负电源生成电路,产生-3 V电压用于关断低侧增强型GaN功率器件,同时生成用于高侧自举电路开启充电管的电压。本文设计的芯片设置了保护电路,提高驱动芯片的可靠性。本文基于0.18μm 40 V BCD工艺,对设计的驱动芯片电路进行设计和仿真验证,同时进行了版图规划和后仿验证。本文设计的驱动芯片的传输延时在10 ns左右,并且高低两侧通道的传输延时小于4 ns,驱动芯片的CMTI能力超过30 V/ns,输入驱动信号峰值14 V,开关频率达到1 MHz以上,电源轨稳定建立,驱动芯片输出信号稳定。更多还原

【Abstract】 GaN as a third-generation semiconductor has developed rapidly in recent years,because it can achieve higher switching frequency and more efficient power supply and has been gradually applied in various fields.Compared with Si-based devices,enhancement mode GaN devices have lower on-resistance and faster switching frequency,which puts forward higher requirements for their gate drive performance.Therefore,it is of great significance to study the gate drive chips of enhancement mode GaN power devices.Enhancement-mode GaN power devices are often used in high-frequency applications due to their high saturation velocity characteristics.However,when designing GaN-based high-frequency drive circuits,three major problems need to be addressed.1)When designing the gate driver chip of the enhancement mode GaN power device with the half-bridge structure,the CMTI capability is unsatisfied,due to a large dv/dt generated during the fast switching process;2)the propagation delay is large and the matching is poor;3)During the switching process,problems such as negative pressure will be generated at the junction.In this thesis,a driver chip for enhancement mode GaN power devices is designed to detect and limit the input signal,and remove the influence of factors such as burrs from outside the chip.Multiple power rails are designed to drive the normal operation inside the chip.For the dv/dt problem,when designing the level shift circuit,this thesis proposes a method of bypassing the positive and negative feedback circuits to further improve the common mode transient immunity(CMTI)capability;for the transmission delay and matching problems,Use the input detection circuit to limit the input signal to1.8 V,so that a level shift circuit similar to the high-side signal transmission channel can also be designed in the low-side signal transmission channel,try to use low-voltage devices in the chip to reduce the RC delay,and design a high-speed level shift circuit controlled by short pulses to reduce the transmission delay and reduce power consumption.In view of the problem of negative voltage,in the high-side channel,this thesis voltage to use a negative pressure detection circuit on the basis of avoiding the dead time charging is proposed,to double ensure that the node is free from negative pressure,and the charging PMOS transistor is replaced to a NMOS transistor to improve charging.current and avoid insufficient charging;when the low-side negative voltage occurs,this thesis proposes to use a positive and negative power generation circuit to generate-3 V voltage to turn off the low-side enhancement mode GaN power device,and generate a high-side bootstrap circuit at the same time.Turn on the voltage of the charging tube.The chip designed in this thesis is equipped with a protection circuit to improve the reliability of the driver chip.Based on the 0.18 μm 40 V BCD process,the designed driver chip circuit is designed in this thesis,and the layout planning and post-simulation verification are conducted.The transmission delay of the driver chip designed in this thesis is about 10 ns,and the transmission delay of the high and low channels is less than 4 ns.The CMTI capability of the driver chip exceeds 30 V/ns,the peak value of the input driving signal is 14 V,and the switching frequency reaches more than 1 MHz.The power rail is established stably,and the output signal of the driver chip is stable.更多还原