【作者】 刘旭东；

【导师】 杨军； 王镇；

【作者基本信息】 东南大学 ， 集成电路工程（专业学位）， 2021， 硕士

【摘要】 近年来,物联网(Internet of things,Io T)技术蓬勃发展,为了满足物联网设备高能效的需求,电压低至近阈值区域的片上系统(System on a Chip,So C)正逐渐成为研究的热点。静态随机存取存储器(Static Random Access Memory,SRAM)作为So C的重要组成部分,其存储阵列通常是由最小尺寸的晶体管组成的,小尺寸高密度导致其在低电压下性能的退化与逻辑电路相比更加严重,低电压下SRAM的速度已经成为芯片性能的瓶颈。针对在低电压下SRAM性能退化严重的问题,在SRAM中使用流水线技术可以提高其读写操作速度,然而现有的流水线型SRAM技术存在时序切分不均匀的问题,这会使时钟频率受到过长的位线放电时间的限制,从而限制了流水线技术在SRAM中的应用。本文提出了一种改进的流水线型SRAM时序切分方案,该方案允许位线放电延时占用更多的时钟周期,从而实现了时钟频率的进一步提升。针对由改进的流水线型SRAM时序切分方案导致的字线交叠问题,本文分别就连续读取操作、连续写入操作以及先读后写操作和先写后读操作四种情况进行了讨论,提出了双字线存储单元方案来解决连续读操作中存在的问题,提出了写跟踪方案来解决连续写操作和写后读操作中存在的问题,提出了空闲周期方案以解决读后写操作中存在的问题,并在文中就以上解决方案分别给出了具体的电路实现。本文基于TSMC 22nm工艺,设计了容量为512×32的流水线型SRAM及其版图,后仿真结果表明,该方案可以有效地提高电路的性能。在低电压0.6V下,本方案的最大时钟频率和功耗延迟积与传统SRAM相比分别改善了1.91倍和34.2%;在常规电压0.9V下,本方案的最大时钟频率和功耗延迟积与传统SRAM相比分别改善了2.4倍和45.5%。与近年发表的同类文献相比,本文方案同样具有更好的性能提升。更多还原

【Abstract】 In recent years,the Internet of things(Io T)technology has developed vigorously.In order to meet the high energy efficiency requirements of Io T devices,System on a Chip(So C)with a voltage as low as near the threshold region is gradually becoming a research hotspot.Static random access memory(SRAM)is an important part of So C.Its memory array is usually composed of the smallest size transistors.The small size and high density cause the degradation of its performance under low voltage to be more serious than that of logic circuits.The speed of SRAM under low voltage has become the bottleneck of chip performance.In view of the serious degradation of SRAM performance under low voltage,the use of pipeline technology in SRAM can increase the speed of its read and write operations.The timing of the existing pipeline scheme is not evenly divided,so that the clock frequency is limited by the excessively long bit line discharge time,thereby limiting the application of the pipeline technology in the SRAM.An improved pipelined SRAM timing segmentation scheme is proposed in this article,which allows the bit line discharge delay to occupy more clock cycles,thereby achieving a further increase in clock frequency.In view of the word line overlap problem caused by the improved pipelined SRAM timing splitting scheme,the four situations of continuous read operation,continuous write operation,write-after-read operation and writeafter-read operation are discussed in this article,respectively.The dual word line bitcell scheme was proposed to solve the problems in continuous read operations,the write tracking scheme was proposed to solve the problems in continuous write operations and read-after-write operations,and the idle cycle scheme was proposed to solve the problems in write-after-read operations.The specific circuit implementations of the above solutions are given in the article.Based on the TSMC 22 nm process,a pipelined SRAM with a capacity of 512×32 and its layout are designed in this article.The post-simulation results show that this scheme can effectively improve the performance of the circuit.At a low voltage of 0.6V,the maximum clock frequency and power consumption delay product of this solution are improved by 1.91 times and 34.2% respectively compared with traditional SRAM;Under the normal voltage of 0.9V,the maximum clock frequency and power consumption delay product of this solution are improved by 2.4 times and 45.5% respectively compared with traditional SRAM.Compared with similar documents published in recent years,the solution in this article also has a better performance improvement.更多还原