【作者】 雷雨田；

【导师】 李哲涛；

【作者基本信息】 湘潭大学 ， 计算机科学与技术， 2021， 硕士

【摘要】 随着人工智能技术的不断发展,卷积神经网络已经广泛地用于解决各种复杂问题,并在学术界和工业界引起了大量的关注。在物联网技术的推动下,卷积神经网络也开始应用于各种嵌入式和移动设备,用来实现各种智能功能。在这些应用场景中,FPGA特别适合用来加速卷积神经网络的计算,因为其具有高性能、低时延、低功耗以及开发周期短等优点。为了解决卷积神经网络大量的参数和计算量所带来的限制,同时满足多样化的卷积神经网络结构,研究者在FPGA上设计了深度学习处理单元(DPU)用于对卷积神经网络的通用加速。目前DPU的加速方案存在着DPU利用率和DPU调度效率低的问题,本文针对这两个问题分别提出了MCDS加速方案和DPU Plus加速方案。本文主要研究内容如下:1.对于卷积神经网络在FPGA上的硬件实现,本文使用了Xilinx提供的DPU加速方案。该方案中的DPU是一种通用的卷积神经网络加速器,通过与软件工具配合,DPU可以完成对各种卷积神经网络模型的加速计算。本文使用该方案完成了几个常用的卷积神经网络模型的硬件实现,同时使用这几个卷积神经网络模型去执行智能交通场景下的智能任务,并达到了一定的检测速度与精度。2.对于在DPU上执行卷积神经网络模型时DPU利用率低的问题,本文提出了MCDS加速方案。该方案旨在硬件资源有限的FPGA上,设计多个不同尺寸的DPU核。本文完成了不同尺寸DPU核的硬件实现,并测试了几个常用卷积神经网络模型在不同尺寸DPU核上的DPU利用率和FPS。实验数据表明,与Xilinx提供的DPU加速方案相比,MCDS加速方案有效地提升了DPU利用率和DPU核数量,从而提升了DPU的整体吞吐量,达到加速计算的效果。3.对于卷积神经网络模型的应用系统中的DPU调度效率低的问题,本文提出了DPU Plus加速方案。该方案旨在FPGA上同时实现DPU核和辅助模块,并让两者能够共同完成计算任务。DPU Plus加速方案是一种通用的硬件设计方案,其充分利用了FPGA的高性能和灵活性。通过制作流程的创新,本文完成了DPU Plus的一种硬件实现,并基于此硬件开发了上层应用系统。实验数据表明,与Xilinx提供的DPU加速方案相比,DPU Plus加速方案能有效地提高DPU调度效率,从而提升了应用系统的整体吞吐量,达到加速计算的效果。更多还原

【Abstract】 With the continuous development of artificial intelligence technology,convolutional neural networks have been widely used to solve various complex problems,and have attracted a lot of attention in academia and industry.Driven by the internet of things technology,convolutional neural networks have also begun to be applied to various embedded and mobile devices to implement various intelligent functions.In these application scenarios,FPGAs are particularly suitable for accelerating the calculation of convolutional neural networks because of their high performance,low latency,low power consumption,and short development cycle.In order to solve the limitations brought by the large number of parameters and calculations of the convolutional neural network,and to meet the diversified convolutional neural network structure,the researchers designed a deep learning processing unit(DPU)on the FPGA for the convolutional neural network universal acceleration.The current DPU acceleration scheme has the problems of low DPU utilization and DPU scheduling efficiency.This article proposes the MCDS acceleration scheme and the DPU Plus acceleration scheme for these two problems.The main research contents of this paper are as follows:1.For the hardware implementation of convolutional neural network on FPGA,this article uses the DPU acceleration scheme provided by Xilinx.The DPU in this scheme is a general convolutional neural network accelerator.By cooperating with software tools,the DPU can complete the accelerated calculation of various convolutional neural network models.This paper uses this scheme to complete the hardware implementation of several commonly used convolutional neural network models,and at the same time uses these convolutional neural network models to perform intelligent tasks in intelligent transportation scenarios,and achieves a certain detection speed and accuracy.2.For the problem of low DPU utilization when executing the convolutional neural network model on the DPU,this paper proposes an MCDS acceleration scheme.This solution aims to design multiple DPU cores of different sizes on FPGAs with limited hardware resources.This paper has completed the hardware implementation of DPU cores of different sizes,and tested the DPU utilization and FPS of several commonly used convolutional neural network models on DPU cores of different sizes.Experimental data shows that compared with the DPU acceleration scheme provided by Xilinx,the MCDS acceleration scheme effectively improves the DPU utilization rate and the number of DPU cores,thereby increasing the overall throughput of the DPU and achieving the effect of accelerating calculations.3.For the problem of low DPU scheduling efficiency in the application system of the convolutional neural network model,this paper proposes a DPU Plus acceleration scheme.This solution aims to implement the DPU core and auxiliary modules on the FPGA at the same time,and allow the two modules to complete computing tasks together.The DPU Plus acceleration scheme is a general hardware design scheme,which makes full use of the high performance and flexibility of FPGA.Through the innovation of the production process,this paper has completed a hardware realization of DPU Plus,and developed the upper application system based on this hardware.Experimental data shows that compared with the DPU acceleration solution provided by Xilinx,the DPU Plus acceleration solution can effectively improve the DPU scheduling efficiency,thereby increasing the overall throughput of the application system and achieving the effect of accelerating calculations.更多还原