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面向SOC供电具有低FOM值的低压差线性稳压器的研究与设计
Research and Design of Low-dropout Regulator with Low FOM for SoC Power Supply
【作者】 张杰;
【导师】 明鑫;
【作者基本信息】 电子科技大学 , 微电子学与固体电子学, 2021, 硕士
【摘要】 低压差线性稳压器(Low Dropout Regulator,简称LDO)具有占用芯片面积小、外围器件简单、低功耗、高精度和低噪声等特点,被广泛的应用于片上SoC供电的场景中。片上SoC的电路模块往往对供电电源电压十分敏感,并且随着时钟高低电平的快速切换,这些模块会从电源中高频率的抽取电流,导致电源电压发生波动,这可能会导致模块工作状态异常。为了应对这种高频率、大电流的负载跳变的情况,并高效地给SoC供给持续、稳定的电压,需要LDO具有瞬态响应速度快、带载能力强、静态电流小等特点,即需要LDO具有较低的优良指数(figure of merit,简称FOM)。本文内容主要涉及对低FOM值的LDO的研究与设计。通过研究分析LDO的基本原理和SoC的供电需求,本文设计了3款具有低FOM值的LDO,3款电路均在0.35um CMOS工艺平台下进行了流片和后期测试。第一款LDO的功率管为NMOS,采用双电源供电模式,不需要额外的电荷泵来驱动功率管。通过电流回收和有源箝位技术,可以在不降低系统电流效率的情况下提升环路带宽和高频负载跳变时的瞬态响应速度。得益于自适应频率补偿技术,环路在全负载范围内都能保持足够的稳定性。第二款LDO同样采用NMOS作为功率管,通过采用过冲消散技术,该LDO可以对瞬态跳变时输出电压过冲进行快速泄放,快速稳定输出电压。此外,通过采用浮动地缓冲器作为LDO的第二级缓冲器,可以有效提高功率管栅极电压的转换速率和LDO环路带宽,加快瞬态响应速度,同时不会降低LDO的电流效率。不仅如此,借助于自适应补偿网络,该LDO可以在不同负载情况下满足良好的稳定性。第三款LDO采用PMOS作为功率管。误差放大器采用了一种先进的电流放大器和动态偏置技术,在不增加静态功率的情况下,可以显著地拓宽环路的带宽,从而大大提高瞬态响应速度。此外,在LDO中嵌入了动态参考电压控制结构(DRC),在瞬态过程中自适应调整参考电压,进一步提高了EA的转换速率,显著提高了EA的瞬态性能。
【Abstract】 Low dropout regulator(LDO)has the characteristics of small chip area,simple peripheral devices,low power consumption,high precision and low noise,and is widely used for SoC Power Supply.Circuits modules in SoC are sensitive to the power supply voltage.With the high-frequency swithing of clock,these modules will generate hightransient-frequency load current,resulting in the fluctuation of input voltage,which may lead to the abnormal working state of the relevant circuit modules.In order to cope with the high-frequency and large-current load transient,and supply continuous and stable voltage efficiently,LDO is required for fast transient response ability,high driving capacity and small quiescent current,that is,LDO is required to have low figure of merit(FOM).The content of this article mainly involves the research and design of LDO with low FOM value.Through the research and analysis of the basic principles of LDO and the power supply requirements of SoC,3 LDOs with low FOM value are designed in this paper,all of which have been taped out under the 0.35 um CMOS process.The power transistor of the first LDO is N-type MOSFET(NMOS).By adopting dual power supply mode,it is not necessary for an additional charge pump to drive the power transistor.With the power recycle and active clamping technology,the loop bandwidth and the transient response speed during high-frequency load transient can be improved without reducing the current efficiency of the system.And thanks to adaptive frequency compensation technology,the LDO loop can maintain sufficient stability under different load conditions.The second LDO also uses NMOS as the power transistor.By adopting the overshoot dissipation technology,the LDO can quickly discharge the output voltage overshoot during transient,and quickly stabilize the output voltage.In addition,by using a floating ground buffer as the second-stage of the LDO,the slew rate of the gate voltage of the power transistor and the loop bandwidth of the LDO can be effectively enhanced,and the transient response speed will be accelerated without reducing the current efficiency of the LDO.Not only that,with the help of an adaptive compensation network,the LDO can meet good stability under different load conditions.The third LDO uses PMOS as the power transistor.The error amplifier(EA)adopts an advanced current amplifier and dynamic bias technology,which can significantly broaden the bandwidth of the loop without increasing the static power,thereby greatly improving the transient response speed.In addition,the dynamic reference voltage control structure(DRC)is embedded in the LDO,and the reference voltage is adaptively adjusted during load transient,which further improves the SR of the EA.
【Key words】 low-dropout regulator; SoC; high-frequency load transient; figure of merit; NMOS;