【作者】 韩涛；

【导师】 张建伟；

【作者基本信息】 大连理工大学 ， 电子科学与技术， 2021， 硕士

【摘要】 FPGA(Field Programmable Gate Array)由于具有灵活的可配置性,被广泛应用于科研及商业领域。其中SRAM型FPGA因其资源丰富、性能强和可重配置等优点,受到航天领域的青睐。但不同于地面环境,空间环境中存在众多辐射效应,包括总剂量效应(Total Ionizing Dose,TID)和单粒子效应(Single Event Effect,SEE)。而SRAM型FPGA因其结构特点对单粒子翻转(Single Event Upset,SEU)效应非常敏感,这极大地限制了其在航空航天领域的应用。SRAM型FPGA的抗辐照技术成为了一个研究热点。三模冗余(Triple Modular Redundancy,TMR)和配置存储器刷新是FPGA抗辐照加固的有效手段,但都有各自的缺点:三模冗余无法修复错误,且当用户电路很大时,会消耗大量资源;配置刷新方法的刷新电路本身对辐射敏感。对此,本文提出了一种实时冗余刷新(Real-time Redundant Scrubbing,RRS)系统,该系统将三模冗余和刷新电路相结合,在传统刷新电路的基础上,对刷新电路本身作三模冗余处理。首先,设计了一个基于SRAM型FPGA的配置存储器刷新系统。该系统通过ICAP(Internal Configuration Access Port)接口按帧回读配置数据,然后利用FRAME＿ECC电路进行ECC校验,若发现1位错误则根据校验信息进行修改,再将修改后的配置数据写回原位置,实现对配置存储器的纠错。其次,对刷新电路进行了三模冗余加固。对传统的三模冗余结构进行了改进,加入了错误指示器。每当有任一冗余块的输出与其他两个不同时,错误指示器就会发出警报,使系统立即对刷新电路进行刷新,从而防止错误累积,并实现了对刷新电路的实时刷新。再次,对刷新电路进行了分布式布局。EDA工具在自动布局布线时会倾向于把相关变量布局在相近位置,此时一个SEU可能会影响多个冗余块,从而使三模冗余结构失效。因此,本文对刷新电路进行了分布式布局,将三模冗余的三个冗余块分离开来。这样,一个SEU就很难同时使两个冗余逻辑发生错误,进一步提高了系统的抗辐照能力。此外,还设计了一个故障注入系统。故障注入系统与刷新系统相似,首先通过ICAP接口回读某一帧配置数据,然后翻转其中的1位,再写回原位置,以模拟发生SEU的情况。通过故障注入系统可方便灵活地对本文提出的RRS系统进行测试验证。最后,经故障注入测试,本文提出的RRS系统可实现对SRAM型FPGA配置存储器的2位检错和1位纠错,尽管面积是传统配置存储器刷新系统的3倍左右,但资源占用总量很小,与此同时抗辐照能力得到了显著提高。更多还原

【Abstract】 Field Programmable Gate Array(FPGA)is widely used in scientific research and commercial fields because of its flexible configurability.SRAM-based FPGA is favored by aerospace field because of its rich resources,strong performance and reconfigurable advantages.However,different from the ground environment,there are a lot of radiation effects in the space environment,including the Total Ionizing Dose(TID)and the Single Event Upset(SEE).SRAM-based FPGA is very sensitive to Single Event Upset(SEU)effect because of its structural characteristics,which greatly limits its application in aerospace field.The antiradiation technology of SRAM-based FPGA has become a hot research topic.Triple Modular Redundancy(TMR)and configuration memory scrubbing are effective methods of FPGA radiation protection,but each has its own shortcomings: TMR structure can’t correct errors,and when user circuits are very large,a lot of resources will be consumed;scrub circuit of scrubbing method itself is sensitive to radiation.In this regard,this paper proposes a Real-time Redundant Scrubbing(RRS)system,which combines TMR structure and scrub circuit.Based on the traditional configuration scrubbing,TMR structure is applied to the scrubber.Firstly,a configuration memory scrubbing system on SRAM-based FPGA is designed.The system reads back configuration data by frame through Internal Configuration Access Port(ICAP),and then uses the FRAME＿ECC circuit to perform ECC verification.If a 1-bit error is found,modify it according to the verification information,and then write the correct configuration data back to the original location to realize the error correction of the configuration memory.Secondly,the scrub circuit has been hardened with TMR.The traditional TMR structure has been improved,and an error indicator has been added.Whenever the output of any redundant block is different from the other two,the error indicator will give an alarm,so that the system scrubs the scrub circuit immediately,thereby preventing the accumulation of errors and realizing the real-time scrub of the scrub circuit.Thirdly,a distributed floorplan is performed on the scrub circuit.The EDA tool tends to lay the relevant variables in a similar position when the floorplan is automatic.At this time,one SEU may affect multiple redundant blocks,which will invalidate the TMR structure.Therefore,this paper has carried out a distributed floorplan on the scrub circuit,separating the three redundant blocks of TMR.In this way,it is difficult for one SEU to make two redundant logic errors at the same time,which further improves the system’s anti-radiation capability.In addition,a fault injection system is designed.The fault injection system is similar to the scrubbing system.Firstly,the configuration data of a frame is read back through the ICAP interface,and then one bit of the frame is flipped and written back to the original position to simulate the SEU.The RRS system designed in this paper can be easily and flexibly tested and verified by fault injection system.After verification,the proposed RRS system can realize 2-bit error detection and 1-bit error correction of FPGA configuration memory.Although the area is about 3 times of that of traditional configuration memory scrubbing system,the total amount of resources occupied is very small,and the anti-radiation capability ability has been significantly improved.更多还原