【作者】 郭浩；

【导师】 李海华； 陈宏璘；

【作者基本信息】 上海交通大学 ， 集成电路工程（专业学位）， 2019， 硕士

【摘要】 随着技术节点按照摩尔定律持续降低,特征尺寸进一步缩小,后段集成工艺普遍引入低介电介质材料的多层铜互连工艺以降低Rc延迟带来的影响,但同时也带来了更为复杂的制造工艺。集成电路不断往高密度的方向发展也使得芯片对缺陷的容忍度越来越低,缺陷问题成为良率损失的主要原因之一。本文针对笔者所在公司55纳米平台铜互连工艺的主要系统性缺陷问题进行了深入研究,提出了有效的改善方案。其中针对薄膜工艺造成的晶边剥落缺陷问题,通过合理选择搭配暗场缺陷检测偏振过滤和傅里叶过滤技术,解决了Cu hillock带来的干扰。采用湿法清洗晶背的方式将缺陷数量降低了83%。并优化了基准工艺条件,使用新工艺条件清洗10次后光刻找平数据范围改善了95%。针对电镀铜工艺造成的空洞问题,创新的引入了NDC后的亮场缺陷检测,解决了因为长时间等待造成的铜结晶带来的干扰。实验数据表明较薄的阻挡层配合较厚的种子层,可以满足后续电镀铜对阻挡层和种子层的台阶覆盖要求。进入阶段高电流密度的稳定性和更强的添加剂,都可以提高铜填充能力。新工艺条件下缺陷改善了67%。针对铜研磨工艺造成的晶边失焦问题,采取了增加网格图形密度修复方式修复版图热点,扩大了CMP工艺窗口。同时优化了研磨头压力参数,新工艺条件的缺陷数量改善了83%。以上技术难题的研究和解决,不但提升了产品良率,更进一步提升了公司55纳米工艺平台的健康度。问题研究中提出的改善方向和解决方法也为公司28纳米工艺的研发提供了宝贵的资料,具有重要的参考意义。更多还原

【Abstract】 As the technology nodes continue to decrease according to Moore’s Law,the feature size is further reduced.The BEOL process generally introduces multilayer copper interconnect processes and low dielectric materials to reduce the impact of RC delay,which also make the processes complicated.The continuous development of integrated circuits in the direction of high density makes the chip’s tolerance to defects become lower and lower,and the defect problem becomes one of the main reasons for the loss of yield.In this paper,the main systematic defects of copper interconnect process at 55 nm platform in the company are studied in depth,and an effective improvement scheme is proposed.In order to solve the problem of peeling defects in wafer edge caused by the thin film process,the interference caused by Cu hillock is solved by reasonable selection and matching of dark field defect detection polarization filtering and Fourier filtering technology.The number of defects was reduced by 83% by adding wet cleaning on the backside of wafer.The benchmark process conditions were optimized and the lithography leveling data range was improved by95% after 10 times of cleanings using the new process conditions.In view of the void defects caused by the electroplating copper process,bright field after NDC DEP has been introduced to solve the interference caused by copper crystallization.The experimental data showed that the thinner barrier layer was combined with the thicker seed layer to meet the step coverage requirements.The high current density stability and stronger additives can increase the copper filling capacity.The defect was improved by 67% by using the new process conditions.In order to solve the defocusing in wafer edge caused by copper grinding process,the grid pattern density repair method was adopted to repair the layout hotspot,and the CMP process window was expanded.With the optimization of the grinding head pressure parameters,the number of defects in the new process conditions improved by 83%.The research and solution of the above technical problems not only improved the yield of products,but also further improved the quality of the55 nm process platform.The improvement directions and solutions proposed in the problem research also provide valuable information for the research and development of 28 nm process in my company.更多还原