【作者】 陈辉；

【导师】 潘红兵；

【作者基本信息】 南京大学 ， 集成电路工程（专业学位）， 2016， 硕士

【摘要】 快速傅里叶变换(FFT)在数字信号处理中起着至关重要的作用,随着FFT在雷达信号处理、信息通信等应用领域上的不断普及,FFT被要求拥有不同的实现算法和实现架构,其应用不断地向高吞吐率、高精度、实时性强和通用性高等方向发展,特别是正交频分复用(OFDM)技术的兴起对FFT处理器的灵活性提出了更高的要求。因此研究和设计出高速、高精度、通用性强的FFT硬件加速器或处理器具有很强的实际意义。本文详细阐述了一种混合基FFT硬件加速器的设计以及实现,通过对FFT的不同算法和硬件实现结构的分析比较,选择混合基(Radix-2/4)FFT算法和SDF流水线的硬件结构来实现可变点FFT硬件加速器。在算法设计上选择Radix-4FFT算法为主体,Radix-2算法为辅,这减少了FFT的乘法运算量,同时还提高了 FFT的运算精度。此外本文还改进了 Radix-4算法的SDF结构,进一步优化了加速器设计,降低了控制程序的复杂度。在结构设计上选择采用SDF流水线结构,这种实现方式可以利用相对较少的硬件资源设计出实时处理能力强的FFT硬件加速器。为了获得加速器的通用性,该加速器支持可变点数配置,通过配置模式选择寄存器的值可以让该加速器工作在64、128、256、512和1024点模式下。同时为了提高资源的利用率,每条反馈路径被设计成了可以工作在全深度和半深度两种工作模式下。此外,同一个ROM中存储的旋转因子可以为两种不同的点数模式复用,同时ROM的寻址计数器也可以复用;最后一级Radix-4算法蝶形可以配置成Radix-2算法蝶形;整序模块中RAM的读写寻址共用同一个寻址计数器等等都体现资源复用的设计思想。MATLAB和ISim的联合仿真证明了本加速器可以得到正确的计算结果,其信噪比(SNR)达到139dB以上,综合结果显示该加速器在Virtex-7 XC7VX485T FPGA中的工作频率可以达到287MHz,1024点FFT的处理时间在11us内,可以满足信号实时处理的要求。更多还原

【Abstract】 Fast Fourier Transform(FFT)plays a crucial role in the field of Digital Signal Processing.With the growing popularity of FFT algorithm,it’s required to have diverse algorithms and architectures for FFT implementation in different application areas,such as Radar Signal Processing and Information Communication filed.Besides that,high throughput,high precision,strong real-time and good universality are new directions for the application of FFT.Especially,the flexibility of FFT processor is further proposed by the development of Orthogonal Frequency Division Multiplexing(ODFM).This paper elaborates the design and implementation of a mixed-radix FFT accelerator.Mixed-radix FFT algorithm and single path delay feedback(SDF)pipeline architecture were used to design the accelerator through the comparison and analysis of different algorithms and hardware implementation schemes of FFT.And the proposed mixed-radix algorithm is based primarily on Radix-2/4 algorithms so that the multiplication could decrease and the operating precision could increase.In addition,this paper also improved the SDF architectures which can further optimal design and reduce the complexity of the control program.For the SDF pipeline,it’s an effective way to design a strong real-time FFT accelerator with fewer resources.To meet good universality,this accelerator is able to execute FFT of size including 64,128,256 and 1024-points in continuous-flow by re-configuring Mode Register.And some special techniques are adopted to make full advantage of resources,for example,each of the feedback paths can work in both full-depth and half-depth modes.In addition,these techniques also including that twiddle factors stored in a ROM block and addressing counter of ROM can be reused for two kinds of different models,the radix-4 butterfly in the last stage can be configured to a radix-2 butterfly,and both read and write addresses of RAM in reorder module are created by an addressing counter.The proposed accelerator has been implemented on a Xilinx device Virtex-7 XC7VX485T and fully tested by the method of co-simulation using MATLAB and ISim simulation software.According to the measured results,the signal-to-noise ratio(SNR)reach up to 139dB.The synthesis results show that the maximum clock frequency can achieve 287MHz and 1024-point FFT is less than 11us,so the design can meet the requirements of real-time.更多还原