【作者】 杨光；

【导师】 韩雁； 莫要武；

【作者基本信息】 浙江大学 ， 集成电路工程， 2020， 硕士

【摘要】 CMOS图像传感器市场正在持续快速增长,在中美贸易战背景下,对于国产CMOS图像传感器厂商而言,当前正处于一个机遇与挑战并存的历史阶段。锁相环和带隙基准源是CMOS图像传感器结构中必不可少的电路模块。锁相环作为片上集成时钟信号发生电路,对CMOS图像传感器的正常工作起着决定性的作用。带隙基准源能够为芯片内部提供具有一定温度系数的电压和电流偏置,同时也为锁相环的电荷泵提供电流输入,是锁相环正常工作必不可少的组成部分,因此电源控制模块和锁相环都是本文的研究内容。本文从CMOS图像传感器的基本结构入手,设计了CMOS图像传感器应用中包括带隙基准源在内的电源模块以及锁相环模块,其中锁相环电路包括了一款单环路电荷泵锁相环和一款创新的双环路电荷泵锁相环。本文总结了具有通用性的带隙基准源和锁相环的一般设计思路和流程,通过修改提出的电路拓扑的特定参数就能够实现在不同工艺下的兼容。上述电源模块和锁相环均在不同代工厂的不同工艺条件下通过流片验证,在不同产品中能够保证CMOS图像传感器芯片的正常工作。本文详细分析了电源控制模块的各电路架构和需求,着重分析了带隙基准源的关注指标和设计原则,设计了符合应用需求的带隙基准源。本文给出所设计的带隙基准源在三家代工厂四种工艺下的后仿真结果,通过了流片验证,并且都已在量产芯片中应用。在设计中我们保证温度系数优先,输出基准电压在1.2V附近。由于篇幅限制,本文设计的锁相环仅给出在DB 0.118)for CIS 1P3M工艺下的技术指标。测试结果表明所设计的单环路电荷泵锁相环和双环路电荷泵锁相环均能够在1.8V和2.8V模拟电源电压以及1.5V和1.8V数字电源电压的电压组合下正常工作。二者均支持6-40MHz的输入参考频率,根据应用场景常用27MHz,通过配置分频比,二者均能够实现0.4-1.5 GHz的调谐范围,后仿真表明压控振荡器在945MHz或者1GHz的振荡频率下在各工艺角下实现48%-52%的占空比。后仿真表明,在945MHz工作频率下:单环路锁相环具有3μs的建立时间,TIE jitter有效值为23.3ps,Period jitter有效值为1.22ps,Long Term jitter有效值为33.5ps,功耗有效值为2.875m W,占用面积为0.0571 mm~2;双环路锁相环具有25μs的建立时间,TIE jitter有效值为18.2ps,Period jitter有效值为1.21ps,Long Term jitter有效值为26.4ps,功耗有效值为3.058m W,占用面积为0.0397 mm~2。本文提出具有创新性的带隙基准源电路拓扑,经过流片验证,能够在三家代工厂四种不同工艺下通过修调特定器件参数的方法达到预期的技术指标,实现工艺兼容。创新地提出双环路锁相环结构,相比于传统的单环路锁相环,其噪声性能更加优异且版图面积节省了约三分之一,大大节省了芯片资源,对降低成本具有非常积极的作用,所提出的双环路锁相环经过仿真和流片验证,确定修调特定器件参数也能够实现工艺兼容。更多还原

【Abstract】 The CMOS image sensor market is growing continuously and rapidly.In the context of the Sino-US trade war,Chinese CMOS image sensor manufacturers are facing huge challenges and in the meantime,opportunities.Phase-locked loops and bandgap reference are essential circuit modules in a CMOS image sensor.The phase-locked loop plays a decisive role in the operation of the CMOS image sensor as an on-chip integrated clock signal generating circuit.The bandgap reference can provide voltage and current bias with a certain temperature coefficient for the chip,and also provide a current source for the phase-locked loop charge pump.It is an essential part for the normal operation of the phase-locked loop,so the power control module and the phase-locked loop are the research content of this paper.This paper starts with the basic structure of a CMOS image sensor,then designs a power control module including a bandgap reference and a phase-locked loop module in CMOS image sensor application.The proposed phase-locked loop circuit includes a single-loop charge pump phase-locked loop And a dual-loop charge pump phase-locked loop.This paper summarizes the general design concerns and procedures of universal bandgap reference and phase-locked loop.By modifying specific parameters of the proposed circuit topology,compatibility in different processes can be achieved.The power control module and phase-locked loops mentioned above have been tested under different process conditions at different foundries,and can guarantee the operation of CMOS image sensor chips in different products.This paper analyzes the circuit architecture and requirements of the power control module in detail and analyzes the indicators we need to focus on and design principles of the bandgap reference,and thus designs a bandgap reference that meets the application requirements.This paper gives the post-simulation results of the designed bandgap reference source under four process conditions of three foundries,which have taped-out and shown no bad effect on sensor operation.They have been applied in mass production chips.In this design,we ensure that the temperature coefficient is the first order priority,and make sure the output reference voltage is around 1.2V.As the length limit,this paper only gives the technical specifications of the designed phase-locked loop under the DB 0.11μm for CIS 1P3M process.The whole CMOS image sensor test results show that the designed single-loop charge pump phase-locked loop and dual-loop charge pump phase-locked loop can work normally under the voltage combination of 1.8V or 2.8V analog power supply voltage and 1.5V or 1.8V digital power supply voltage.Both of them support 6-40MHz input reference frequency.According to the application scenario,27MHz is commonly used.By configuring the divider division ratio,both can achieve a tuning range of 0.4-1.5 GHz.Post-simulation shows that the voltage controlled oscillator output 48%-52%duty cycle at any PVT condition at 945MHz or 1GHz oscillation frequency.Post-simulation shows that at a working frequency of 945MHz,the single-loop phase-locked loop has a settle time of 3μs,the RMS value of TIE jitter is 23.3ps,the RMS value of Period jitter is 1.22ps,the RMS value of Long Term jitter is 33.5ps,the power consumption RMS value is 2.875m W and occupied 0.0571 mm~2 chip area.The dual-loop phase-locked loop has a settling time of 25μs.The RMS value of TIE jitter is18.2ps,the RMS value of Period jitter is 1.21ps,the RMSv alue of Long Term jitter is26.4ps,the power consumption RMS value is 3.058m W and occupied 0.0397 mm~2 chip area.This paper proposes an innovative bandgap reference circuit topology.It can achieve the expected technical indicators by trimming specific device parameters under four different processes at three foundries to achieve process compatibility after tape-out verification.Innovatively proposed a dual-loop PLL structure.Compared with the traditional single-loop PLL,its noise performance is better and the layout area is saved by about one-third,which greatly saves chip resources and is beneficial in reducing costs.The proposed dual-loop PLL can be adjusted to achieve process compatibility by changing the specific device parameters and is verified by both simulation and tape-out.更多还原