【作者】 李佳；

【导师】 张春福； 郭晓龙；

【作者基本信息】 西安电子科技大学 ， 工程硕士（专业学位）， 2020， 硕士

【摘要】 伴随着半导体工艺制造水平的不断进步,电路复杂度、单位面积管子个数和工作频率的不断提高,电路正常工作时的功耗问题不再是集成电路功耗研究领域的唯一重要关注重点,测试时的功耗也逐渐成为必须考虑的问题。由于在电路测试过程中,通常会同时激活大部分逻辑,集成电路在测试时的功耗,特别是峰值功耗,会比正常工作时大得多,这将为电路稳定性、可靠性、测试质量和制造成本等方面带来许多问题。因此,在集成电路的设计和制造阶段如何实现低功耗测试日益重要。在集成电路测试过程中,扫描路径测试结构能够显著提高电路节点的可控性和可测性,被广泛应用。针对上述情况,论文首先对扫描测试过程中的各类功耗、扫描单元(Scan Cell)、扫描链(Scan Chain)、自动测试向量生成(ATPG)过程和测试向量等内容进行了研究。然后,从扫描链和ATPG角度,主要考虑峰值功耗,提出了针对扫描移位过程和扫描捕获过程的低功耗优化方案。最后,使用一种IP核,创建相应扫描链和EDT电路等,在完成基于Primetime PX的功耗仿真环境搭建以后,实现优化方案,分析仿真数据,得到了一定结果。主要的工作和创新之处如下:(1)对于扫描移位过程中,扫描单元和电路功能逻辑中的大量节点会发生翻转,并且持续时间较长,易导致移位功耗占总测试功耗相当大的比例的问题,论文提出了针对扫描移位过程的低功耗优化方案。在实际测试的过程中,需要首先对插入的扫描链结构本身进行测试。一般情况下,当一个IP核被分为多个模块时,插入的扫描链会贯穿并连通所有模块,因而测试过程会产生较大的测试功耗。论文通过给每个模块增加移位时钟控制模块的方案,分块测试,在解决电路结构变化带来的仿真不匹配问题以后,峰值功耗取得约21.74%的优化,平均功耗也有所降低。在针对功能电路的测试过程中,为降低移位过程中同时翻转的电路单元数目,论文提出了错峰测试和在EDT电路中增加低功耗逻辑对测试向量进行优化的方案。通过错峰测试,同时翻转的电路单元被区分开,峰值功耗最大时优化了15.60%。通过低功耗逻辑给无关位指定固定数值,优化测试向量,峰值功耗最高达到17.88%的优化。(2)当集成电路规模较大时,捕获过程也会产生较大的测试功耗。论文提出一种对IP核内部模块中不同电路的测试响应分时捕获的方案。针对捕获时钟的不同来源,通过配置不同的测试向量生成环境,调整捕获时刻,捕获过程的峰值功耗达到了最高12.20%的优化。对于单个时钟控制电路的测试响应捕获过程,论文提出了借助EDT电路进行测试向量控制与筛选的方案。通过借助门控时钟单元产生测试向量和借助EDA工具进行测试向量筛选,捕获过程中的峰值功耗最高可优化79.13%。此时的优化效果与电路结构密切相关。(3)对比优化前后的功耗数据,并结合测试向量的数量、测试覆盖率、信号翻转率、扫描结构和IP核电路结构,论文对每种方案的优劣进行了讨论。论文提出的优化方案均具备较好的实用性和可拓展性,能够对集成电路测试过程中扫描移位和捕获时的功耗,特别是峰值功耗,在一定程度上有所优化。更多还原

【Abstract】 With the continuous progress of semiconductor manufacturing processes,and the increasing in the complexity of the circuit,the numbers of transistors per unit area and the frequency of operating,the issue of power during normal operation is no longer the only important focus in the field of integrated circuit power research,and the power during testing has become an issue that must be more and more considered.Because most of the logic circuits are usually evoked at the same time,the test power of the integrated circuit,especially for the peak power,will be much bigger than the normal operation power,which will cause many issues in terms of stability,reliability,test quality and manufacturing cost.Therefore,how to achieve low power test during the design and manufacturing stages of integrated circuits is becoming an increasingly important issue.Scan structure can improve the controllability and observability of internal nodes of the circuit during the test,which is widely used for its structured feasibility design method.In view of the above situation,the dissertation firstly discusses the various power,scan cells,scan chain,automatic test pattern generation,test pattern and so on in scan test.Secondly,from the perspective of scan chain and ATPG,the schemes with low power optimization are proposed for the scanning shift process and the scanning capture process,especially for the peak power.Finally,an IP core was used to create the corresponding circuits.Primetime PX power analysis tool was used to build a power simulation environment,and the proposed power optimization scheme was implemented,simulated,debugged and analyzed.The main work and innovations are as follows:(1)Aiming at the problem that during the scan shift process,a large number of nodes in the scan unit and logic circuits are flipped,as well as the duration is long,which causes the shift power to account for a considerable proportion of the total test power,the dissertation proposes a low power optimization method.In the scan test process,the inserted scan chain itself needs to be tested first.The scan chain usually runs through all the modules.And the test process will generate large test power.When an IP core is divided into multiple modules,by adding a shifting clock control block to each module and testing the module in a time-sharing manner,the dissertation optimizes the peak power by about 21.74% after solving the problems of simulation mismatch caused by the changes in the circuit structure,and the average power is also reduced.In the process of testing for functional circuits,in order to reduce the numbers of circuit units that are simultaneously flipped during the shift process,the dissertation proposes a method of peak shift test and the optimization of test patterns by EDT circuits as well.Through the peak shift test,the peak power was optimized by 15.60%.By assigning fixed values to the irrelevant bits and optimizing the test pattern,the peak power reaches about 17.88% optimization.(2)When the scale of the integrated circuit is large,the capture process will also generate large test power.The dissertation proposes a time-sharing capture scheme for different circuits testing in the internal modules of the IP core.For different sources of the capture clock,by configuring different test pattern generation environments,the peak power of the capture process was optimized by 12.20%.For capturing the test response under single clock control,the dissertation proposes a method of test pattern control and screening pattern with the help of EDT circuit.By generating test patterns with the clock gating unit and screening test pattern with the EDA tool,the peak power during the capture process an be optimized up to 79.13%.This optimization effect is closely related to the circuit structure.(3)Comparing the power data before and after optimization,the dissertation discusses the advantages and disadvantage of each scheme in combination with the number of test patterns,test coverage,the scanning unit structure and the circuit structure in the IP core.The optimization schemes proposed in this dissertation have great practicality and scalability,which can optimize the power,especially for the peak power,to a certain extent during scan shift and capture in the chip test process.更多还原