【作者】 王艳；

【导师】 黄光明； 高超嵩；

【作者基本信息】 华中师范大学 ， 电路与系统， 2020， 硕士

【摘要】 正在俄罗斯杜布纳联合核研究所(JINR)新建的重离子超导同步加速器(NICA)及其上的多功能探测器(MPD)主要用于研究高重子密度的夸克-胶子等离子体,其能量介于高、低能区之间。NICA/MPD探测器中设计了一套高效电磁量能器(ECal)系统来精确测量与鉴别重离子反应中产生的光子、电子、轻子对和中性介子,为提高鉴别这些粒子的能力,必须提高ECal的时间测量分辨率。基于该目标,本文设计了一款开关电容阵列(Switched Capacitor Arrays,SCAs)型波形采样芯片,用以对ECal探测器的时间进行高精度测量。主要研究内容为:设计了一款4通道基于开关电容阵列的高速波形采样芯片,每个通道由采样保持电路、采样时钟产生电路和读出控制电路三个部分组成,其中采样保持电路由256个采样开关和采样电容组成。采样开关选用传输门加虚拟管的结构,以减小沟道电荷注入和时钟馈通的影响,通过优化组成传输门的N型和P型晶体管尺寸,使得整个输入动态范围内其导通电阻均较小。采样电容选用MOS管电容,减小了芯片面积、提高了芯片集成度。采样时钟产生电路由延时锁相环(Delay-Locked Loop,DLL)和脉宽调整电路组成,而DLL电路的主要单元有压控延时链、鉴相器、电荷泵、环路滤波器以及启动电路。读出控制电路由源跟随器和移位寄存器组成,以实现采样信号的串行化输出。版图的布局布线采用了屏蔽技术和增加线宽的方法来减小走线的寄生电阻和电容,从而提高模拟输入带宽。整体芯片版图参数提取后进行了仿真验证,仿真结果表明:该芯片的采样率在800M-2Gsps高速范围内可调,瞬态平均功耗为0.24mW,输入动态范围为500mV,时间分辨率达63.76ps。芯片面积为2.97mm × 1.5mm。设计了该芯片的测试系统。该系统由芯片绑定板、母板、AD采样板、HPDAQmini数据获取板组成,其中绑定板用于芯片引脚的绑线,并对电源滤波降噪,且能输出4个通道模拟信号。绑定板采用PCIE插件与母板相接;HPDAQmini板实现了芯片基本配置和数据采样传输功能。芯片初步测试结果显示:该芯片实现了高速采样,且系统噪声和时间测量精度均达到设计要求。更多还原

【Abstract】 The heavy ion superconducting synchrotron(NICA)and its multifunctional detector(MPD),which are being built at the Joint Nuclear Research Institute(JINR)in Dubna,Russia,are mainly used to study quark-gluon plasma with high baryon density.The energy is between high and low energy regions.The NICA/MPD detector is designed with a high-efficiency electromagnetic calorimeter(ECal)system to accurately measure and identify the photon,electron,lepton pair and neutral meson generated in the reaction of heavy ions.In order to improve the ability to identify these particles,The time measurement resolution of ECal must be improved.Based on this goal,this paper designs a switched capacitor array(Switched Capacitor Arrays,SCAs)type waveform sampling chip to measure the time of the ECal detector with high precision.The main research contents are:A 4-channel high-speed waveform sampling chip based on a switched capacitor array is designed.Each channel is composed of a sample-and-hold circuit,a sampling clock generation circuit,and a readout control circuit.The sample-and-hold circuit consists of 256 sampling switches and sampling capacitors.composition.The sampling switch selects the structure of the transmission gate and the virtual tube to reduce the influence of channel charge injection and clock feedthrough.By optimizing the size of the N-type and P-type transistors that constitute the transmission gate,the on-resistance of the entire input dynamic range is uniform Smaller.Sampling capacitors use MOS tube capacitors to reduce chip area and improve chip integration.The sampling clock generation circuit is composed of a delay-locked loop(DLL)and a pulse width adjustment circuit,and the main units of the DLL circuit are a voltage-controlled delay chain,a phase detector,a charge pump,a loop filter,and Start the circuit.The readout control circuit is composed of a source follower and a shift register to realize the serialized output of the sampling signal.The layout uses shielding technology and a method of increasing the line width to reduce the parasitic resistance and capacitance of the trace,thereby increasing the analog input bandwidth.The overall chip layout parameters were extracted and verified by simulation.The simulation results show that the sampling rate of the chip is adjustable in the high-speed range of 800M-2Gsps,the transient average power consumption is 0.24mW,the input dynamic range is 500mV,and the time resolution is 63.76ps.The chip area is 2.97mm x 1.5mm.The test system of the chip is designed.The system is composed of a chip binding board,a motherboard,an AD sampling board,and a HPDAQmini data acquisition board.The binding board is used to bind the chip pins,filter and reduce noise on the power supply,and output 4 channels of analog signals.The binding board uses PCIE plug-in to connect with the motherboard;the HPDAQmini board realizes the basic configuration of the chip and the function of data sampling and transmission.The preliminary test results of the chip show that the chip achieves high-speed sampling,and the system noise and time measurement accuracy meet the design requirements.更多还原