【作者】 李璐；

【导师】 田书林；

【作者基本信息】 电子科技大学 ， 工程硕士（专业学位）， 2020， 硕士

【摘要】 当今通信领域中的高端系统要求时钟信号具备极低的噪声和完整性。抖动是时钟信号的重要时域参数,相位噪声是它的频域等效,它的好坏会严重影响现代数字系统的性能。且现代仪器对于宽频时钟的需求也越来越高。因此对宽频带低抖动时钟发生器的研究具有重要的现实意义。本文围绕宽频带低抖动时钟合成模块展开研究,结合指标要求设计了时钟合成方案,在此基础上实现了硬件电路输出,经调试与测试,达到了50kHz-4GHz的宽频带、5digits的分辨率、低于1ps的时钟抖动指标,其中输出频点1600MHz时相位噪声为-98dBc/Hz@10kHz。主要内容如下:1、时钟抖动的理论研究:首先阐述了抖动的定义和常见的分类,然后推导了抖动与相位噪声的转换关系,为抖动的频域测试与分析提供了理论基础。2、低抖动宽频时钟的合成方案设计:根据课题指标要求,一方面结合课题指标比较了几种频率合成技术,设计了DDS激励PLL的宽频高分辨率时钟合成方案;另一方面结合锁相环的噪声模型和特性,着眼于环路带宽对锁相环输出噪声的影响,设计DDS激励双PLL的宽频带低抖动时钟合成电路设计方案。3、时钟合成模块设计与实现:分析了时钟指标并对其相噪指标进行分级分配,以此来指导芯片选型。采用了恒温晶振为时钟合成模块提供高稳定低底噪的参考时钟;选取了AD9954实现了系统所需的分辨率指标并对其带外滤波器进行了设计;测试了Si9392评估板的性能指标,并对其结构原理、去抖环节和输出配置进行了阐述;选取了ADF4356实现倍频环节并设计了环路滤波器,最后仿真了其相噪性能;选取了ARJ20A4H作为开关切换器件解决了高频带输出切换问题;设计了控制模块,采用MCU+FPGA的控制方式,对其逻辑与驱动程序进行了设计;统计了芯片所需电压与电流,采用DC/DC+LDO对芯片提供电流与电压;最后设计了PCB布局环节,并实现了硬件电路的输出。4、系统调试与测试:阐述了系统的各模块调试过程,在此基础上分析了抖动的时域和频域的测试方法,然后分别对时钟的随机抖动、分辨率与频率准确度指标进行了测试,并对测试结果进行了分析与总结。5、总结与展望:对全文的工作内容作出总结,并从项目研究过程的经验出发,针对存在的缺陷与问题,提出了可以改进的问题和方向。更多还原

【Abstract】 High-end systems in today’s communications field require clock signals with extremely low noise and integrity.Jitter is an important time domain parameter of clock signal,and phase noise is its frequency domain equivalent.And modern instruments for broadband clock demand is also increasing.Therefore,the study of broadband low jitter clock generator has important practical significance.This article revolves around wideband low jitter clock synthesis module study design,combining indicators clock synthesis scheme was designed,on this basis to realize the hardware circuit output,after the debugging and testing,reached 50kHz-4GHz broadband,the resolution of 5 Digits,less than 1 ps of clock jitter indicators,including the output phase noise of frequency 1600MHZ-98dBC/Hz@10kHz.The main contents are as follows:1.Theoretical research on clock jitter: firstly,the definition and common classification of jitter are expounded,and then the conversion relationship between jitter and phase noise is derived,which provides a theoretical basis for frequency domain testing and analysis of jitter.2.Synthesis scheme design of low-dither broadband clock: According to the requirements of the subject index,on the one hand,combining with the subject index to compare several frequency synthesis technologies,design the synthesis scheme of broadband high-resolution clock by DDS driven PLL;On the other hand,combining with the phase noise model of PLL,the noise model and its characteristics are discussed,focusing on the effect of loop bandwidth on the output noise of PLL,the jitter attenuation scheme of double PLL is designed.Finally,the design scheme of broadband low dither clock synthesis circuit with DDS excitation dual PLL is obtained.3.Design and implementation of clock synthesis module: Analyze clock indexes and assign phase noise indexes to guide chip selection.The constant temperature crystal oscillator is used to provide a reference clock with high stability and low bottom noise.AD9954 is selected to realize the resolution index required by the system and its out-of-band filter is designed.The performance index of Si9392 evaluation board is tested,and its structure principle,shaking out link and output configuration are described.ADF4356 is selected to realize frequency doubling and loop filter is designed.Finally,phase noise performance is simulated.ARJ20A4 H is selected as a switching device to solve the high frequency band output switching problem.The control module is designed,and the logic and driver program are designed by using MCU+FPGA.The voltage and current required by the chip are calculated,and DC/DC+LDO is adopted to provide the current and voltage to the chip.Finally,PCB layout is designed and the output of hardware circuit is realized.4.System debugging and testing: the debugging methods of each module of the system are described.On this basis,the testing methods of jitter in time domain and frequency domain are analyzed.Then the random jitter,resolution and frequency accuracy indexes of the clock are tested,and the test results are analyzed.5.Summary and Prospect: Summarize the research and work content of the full text,and based on the experience in the research process of the project,put forward the problems and directions that can be improved.更多还原