【作者】 蒋静；

【导师】 袁焱； 向浩；

【作者基本信息】 上海交通大学 ， 电子与通信工程（专业学位）， 2019， 硕士

【摘要】 无线宽带化、小型密集化是无线通信的发展趋势,LTE Picocell、Femotcell等类似便携设备的需求快速增长。尤其是应急通信场景,更是要求便携,最好是手持,对体积和重量更是提出了严苛的要求。传统的RRU体积大、价格贵,不适合室内密集覆盖场景。当然也有皮站级别的小型收发信机,也就是Pico-RRU,代表性产品有华为公司的Lampsite pRRU和中兴公司的QCell pRRU,但二者的体积和重量都仍然难以满足手持式设备的要求。该项目研制的OFDM宽带收发信机,紧扣小体积、轻重量、低成本的特点,同时按照3GPP要求的技术性能,直击市场需求,填补市场空白点。本项目采用高集成度的AD9361芯片来实现OFDM宽带收发信功能,配合时钟同步电路、低噪声放大电路和控制接口电路一起构建低成本的掌上型LTE收发信机。本项目在如下四个关键技术上进行了研究和开发。1)基于AD9516的时钟同步技术,在AD9516提供初始时钟的基础上,采用FPGA恢复出来自基带板的时钟,并把该恢复时钟送给AD9516,由AD9516切换锁定到该恢复时钟,达到和基带板同步的目的;2)低相位噪声设计技术,首先是低相噪的时钟源选择,其次是干净的电源,关键部位尽量采用LDO供电来压制噪声,最后还有接地和屏蔽设计等考虑;3)高灵敏度接收机设计技术,首先是噪声系数低的LNA选择,其次是合理的前端放大链路规划,最后还有数字模拟地合理分割等优化设计;4)AD9361配置技术,正确的仿真是配置的前提,尽量采用高速SPI来快速配置AD9361。最后,成功地开发完成了原型样机,实现了掌上型、高性能、低成本的设计目标。整个收发信机尺寸约为18cm*10cm*2cm,重量约500克,成本控制在千元以内。关键的体积和重量指标都优于市场同类产品。针对收发信机最关键的技术指标,下行发射机EVM和上行接收机灵敏度,搭建测试环境,得到实测结果:该收发信机单元下行EVM小于3%,优于3GPP要求的8%;10MHz带宽时上行接收机灵敏度优于3GPP要求的-93.5dBm。后续还可以进一步在低噪声电源设计,射频屏蔽设计技术,射频、模拟和数字混合PCB布局布线技术,新型器件优化等方面优化和改进。更多还原

【Abstract】 In high-speed wideband wireless communication,inter-symbol interference(ISI)is a common issue,it occurs when a transmission interferes with itself in multi-path environment,result in receiver decode failure.OFDM can overcome ISI,it is the physical layer core technology of both 4G and 5G.Today,Small size densely deployment and wideband high data rate is the technical trend of wireless communication,the demand of LTE small cell and handheld device increases rapidly espcailly for the indoor coverage,emergency communication and so on.Traditional transceiver is always big,heavy and expensive,even pico-RRU is still too big to fulfill the requirements of small cell or handheld wireless communication device.Focus on the market requirements of small size,light weight and low cost,a kind of handheld wideband OFDM transceiver is designed and implemented in this project,and a real gap in the market is filled.In this project,based on AD9361,a kind of wideband OFDM transceiver core module is designed and implemented;together with clock synchronization circuit,low noise amplifier(LNA)circuit and control & interface circuit,the transceiver is constructed.Four key technical issues are resolved in this project: clock synchronization technology based on AD9516,low noise technology,high sensitivity receiver technology and AD9361 configuration technology.Test is the most important criteria for output quality,the system test environment,method are also defined for this project.Finally a small size,high performance and low cost transceiver sample is released.Its size is 18 cm ~* 10 cm ~* 2cm,weight is about 500g;Downlink EVM is below 3%,better than the requirement of 8% from 3GPP;Uplink receiver Reference sensitive is better than-93.5dBm when 10 MHz bandwidth;and most important,its cost is no more than one thousand RMB.更多还原