【作者】 张辉；

【导师】 杨智明；

【作者基本信息】 哈尔滨工业大学 ， 仪器科学与技术， 2019， 硕士

【摘要】 在遥测遥控应用中,数字通信系统是其不可或缺的重要组成部分,随着对深空探测需求的不断增加,遥测遥控的通信距离越来越远,与地面之间传输的数据量也不断增加,因而对数字通信系统的要求也越来越高。由于遥测遥控系统通信距离远,信号衰减严重,导致通信质量变差,为保证数据有效可靠的传输需要采用高性能的纠错码作为信道编码。低密度校验码（Low-Density Parity-Check Codes,LDPC）由于其接近香农极限的性能,近年来被应用于各种数字通信系统标准中。在LDPC实际应用中,译码器是整个编码译码系统的核心部分,而译码器在译码过程中需要进行大量的计算,为提高译码的速率,保证译码的实时性需合理地设计译码算法的硬件实现方案。针对以上需求,本课题研究CCSDS标准中码长为1408信息位,长度为1024的LDPC码译码器的FPGA实现方法。为实现CCSDS标准下（1408,1024）LDPC码译码器,本文首先研究了CCSDS标准LDPC码的基本原理及具体形式;然后对比研究了三种经典置信度传播译码算法,将分层译码思想与最小和译码算法结合,提出了适用于硬件实现的分层最小和译码算法,并利用MATLAB对其进行算法仿真,分析了算法的纠错性能;为确定译码算法硬件实现时的具体译码参数,本文利用MATLAB对最大迭代次数、量化位数进行了多组仿真实验,分析了上述两种参数对译码性能的影响并确定最终译码器实现时的译码参数;针对译码器FPGA实现时的不同形式,本文对串行架构、全并行架构和部分并行架构三种方案进行对比研究,将分层最小和译码算法与部分并行架构结合,提出了分层部分并行译码器总体架构;以此为基础,依次设计了译码器各个子单元,完成了（1408,1024）LDPC码译码器的FPGA实现。最后,本文利用NI PXIe设备及LabVIEW FPGA开发环境搭建了译码器测试系统,对译码器各项性能进行测试和分析。实际测量结果表明,本文所设计的LDPC译码器最高时钟工作频率为108MHz,在信噪比为3dB时,误码率为10^-6量级,吞吐率达170Mbps。更多还原

【Abstract】 In the application of telemetry remote control,digital communication system is an indispensable and important part.With the increasing demand for deep space exploration,the communication distance of telemetry and remote control is enlarged dramatically,and the amount of data transmitted between flight vehicle and the ground base is also increasing;therefore,the technical requirements for digital communication system has been increased continuously.Due to the long communication distance of the telemetry remote control system and the severe signal attenuation,the communication quality is degraded.In order to guarantee the efficient and reliable transmission of data,a high-performance error correction code is needed as the channel coding.Low-density Parity-Check Codes（LDPC）has been applied to various digital communication system standards due to its performance that is close to shannon’s limits.In practical application,the decoder is the core part of the whole system,and the decoder needs a lot of calculation in the decoding process.In order to guarantee the real-time performance of decoding and improve the decoding rate,it is necessary to design a feasible hardware implementation scheme of decoding algorithm.This paper is to study the FPGA implementation method of LDPC code decoder whose code length is 1408 and information bit length is 1024 under CCSDS standard.In order to implement the（1408,1024）LDPC code decoder under CCSDS standard,this paper firstly studies the basic principle and specific form of CCSDS standard LDPC code,and then compares and studies three classical Belief Propagation decoding algorithms.By combining the layered decoding idea with the minimum sum decoding algorithm,this paper proposes a layered minimum sum decoding algorithm which is suitable for hardware implementation.We use MATLAB to simulate the layered minimum and decoding algorithm,and analyze the error correction performance of the algorithm.Then,in order to determine the specific decoding parameters in the hardware implementation of the decoding algorithm,we use MATLAB to conduct multiple sets of simulation experiments on the maximum number of iterations and quantization digits,and analyze the impact of the above two parameters on the decoding performance and determine the decoding parameters in the final decoder implementation.This paper compares the three schemes of serial architecture,full parallel architecture and partial parallel architecture for the FPGA implementation of LDPC decoder.Based on this,the overall architecture of the layered partial parallel decoder is given by combining the layered minimum sum decoding algorithm with the partial parallel architecture.Then we designe each subunit of the decoder,and complete the FPGA implementation of（1408,1024）LDPC code decoder successively.Finally,we build a decoder test system to test and analyze the performance of the decoder by using the NI PXIe device and the LabVIEW FPGA development environment.Experiment results show that,the maximum clock operating frequency of the LDPC decoder designed in this paper is 108MHz.When the signal-to-noise ratio is3dB,the bit error rate is10^-6 orders and the throughput rate of this decoder is170Mbps.更多还原