【作者】 王珩；

【导师】 常昌远； 晏祥彪；

【作者基本信息】 东南大学 ， 软件工程（专业学位）， 2018， 硕士

【摘要】 计算机网络技术的飞速发展,激励着各个领域的发展。信息的采集工作从少量存储、显示等功能,逐渐变成大量数据采集、实时信号显示及处理等方向发展。因此网络传输不仅局限于局域网而是拓展到城域网和广域网区域。自40G/100G以太网接口标准协议IEEE802.3ba在2010年6月正式发布后,40G/100G以太网产品已被国内外各大公司相继推出,因此对以太网产品的研究无论是在技术层面还是在产业层面都具有很深的意义。本文基于FPGA的工作平台,对40G以太网接口进行设计。主要依据IEEE 802.3ba协议,首先从以太网体系结构,了解接口的组成并通过以太网的数据帧类型、以太网发送与接收规范来实现数据帧的正常传输,并支持全双工通信。然后采用模块化设计将MAC层控制器分为控制器发送模块、控制器接收模块、40G独立媒体接口(40Gb/s Media Independent Interface,XLGMII)模块以及流量控制模块,论文采用Round Robin算法分配、编码的方式来实现40Gb/s的数据发送与接收,并通过XLGMII接口实现数据链路层和物理层的连接。最后,对于传输链路上的拥塞现象通过流量控制策略对数据收发过程进行管理。设计中将每个模块单独阐述,对于复杂模块将其分成若干子模块来论述。设计中均是先给出整个设计总体设计方案,然后分开解读各个模块,内容包括接口信号、状态转换图、流程图、原理图等。本文基于FPGA利用Verilog HDL语言搭建验证平台,对每一个模块的功能进行单独验证,包括收发功能,数据包检测,流量控制等。同时利用Xilinx公司ISE Design Suite工具中的ChipScope,将设计实现FPGA验证,验证结果符合设计要求。本文是基于IEEE802.3ba协议的而设计的40G以太网的接口,并通过FPGA来验证该设计中有较高的互连速度和时钟频率以及更宽更合理的内部并行结构,具有一定的实用意义和经济价值。更多还原

【Abstract】 The rapid development of computer network technology has stimulated the development of various fields.Information collection work from a small amount of storage,display and other functions,gradually become a large number of data acquisition,real-time signal display and processing direction.Therefore,network transmission is not only limited to local area network,but also to metropolitan area network and Wan area.From the beginning of June 2010 for the official release of the standard protocol IEEE802.3ba 40 G / 100 G Ethernet interfaces,the major domestic and foreign companies have been competing to launch 40 G / 100 G Ethernet products.Thus,Ethernet products is of great significance and economic value,and its development without delay.Based on the FPGA platform,this thesis designs the 40 G Ethernet interface.According to the IEEE 802.3 BA protocol,we first understand the composition of the interface from the Ethernet architecture and realize the normal transmission of the data frame through the Ethernet data frame type,Ethernet transmission and reception specifications,and support full duplex communication.Then the MAC layer controller is divided into control sending module,control receiving module,40Gb/s Media Independent Interface(XLGMII)module and flow control module by modular design.Round Robin Scheduling algorithm is used to distribute and encode the data sending and receiving for the speed of 40Gb/s,and XLGMII interface is used to connect the data link layer and physical layer.Finally,congestion on the transmission link is managed by traffic control strategy.Each module is set forth in the design,and it is divided into several sub modules for complex modules.In the design,the overall design scheme is given first,and then each module is interpreted separately,including interface signal,state transition diagram,flow chart,schematic diagram and so on.This thesis uses Verilog HDL language to build a verification platform based on FPGA to verify the functions of each module,including transceiver,packet detection,flow control and so on.At the same time,using ChipScope in Xilinx ISE Design Suite tool,the design is verified by FPGA,and the verification results meet the design requirements.This thesis designs a 40 G Ethernet interface based on the standard protocol IEEE802.3ba,and verifies that the design has higher interconnection speed,clock frequency and wider and more reasonable internal parallel structure by using FPGA.It has certain practical significance and economic value.更多还原