【作者】 李莉；

【导师】 郑光廷； 许达文；

【作者基本信息】 合肥工业大学 ， 微电子学与固体电子学， 2019， 硕士

【摘要】 存储墙问题是限制处理器性能提升的关键问题之一,末级缓存(Last Level Cache,LLC)作为片上系统中容量最大的缓存,是影响处理器性能的关键因素。近年来,COMS的摩尔定律不再延续,碳纳米管场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)由于具有速度快、功耗低的特点,成为CMOS技术的理想替代者之一,它特别适合设计耗电的LLC。然而,目前CNFET的制造过程中存在着严重的工艺偏差(process variation,PV),给基于CNFET的LLC带来巨大的性能损失。为了使基于CNFET的LLC最大限度的发挥出它的潜在优势,本文针对基于CNFET的LLC中的工艺偏差问题提出了一整套完整的解决方案。首先,本文利用LLC的延迟的不对称相关性,对于两种典型的LLC布局(CNT生长方向平行于字线和平行于位线),分别提出了可变延迟的Set(VAS)的LLC和可变延迟的Way(VAW)的LLC。对于VAS LLC,进一步提出了静态页面映射策略,以确保将最常用的虚拟页映射到速度快的缓存区域。类似地,对于VAW缓存,提出了延迟感知的LRU替换策略。此替换策略可以将最近最常用的数据块移动到速度快的缓存区域中。实验结果表明,与传统的基于CNFET的LLC设计相比,本文提出的两种优化后的可变延迟的LLC的性能平均提高了39%并且能耗平均降低了10%。其次,本文针对基于CNFET的非一致性缓存(NUCA)也提出了解决PV问题的方案。对于静态的非一致性缓存(S-NUCA),提出了Bank感知的静态非一致性缓存(BA-SNUCA),它使S-NUCA的每个Bank都是一个可变延迟的缓存。实验结果显示与传统的S-NUCA相比,BA-SNUCA的片上系统的IPC平均增加了7.5%,功耗平均降低了6.8%。对于动态的非一致性缓存(D-NCUA),我们提出了延迟感知的迁移策略。它使经常访问的数据朝着延迟小的Bank迁移。实验结果表明,与传统的逐级晋升的迁移策略相比,具有延迟感知的迁移策略的D-NCUA的片上系统的IPC平均提高了5.9%,功耗平均降低了5.3%。更多还原

【Abstract】 The memory wall is a key issue to limit the performance of processor.And the last-level cache(LLC)with the largest capacity of on-chip cache is one of the most significant factors to affect the performance of processor.In recent years,the Moore’s Law of COMS is no longer extended.The carbon nanotube field effect transistors(CNFET)emerges as a promising alternative to the conventional CMOS for the much higher speed and power efficiency.However,there are serious process variations(PV)in the manufacturing process of CNFETs,which bring huge performance loss to CNFET-based caches.This thesis develops a complete solution for the PV of the CNFET-based LLCs to maximize the potential benefits of itFirstly,for the two typical layouts of LLC(CNT parallel to wordline and CNT parallel to bitline),this thesis utilizes the asymmetry of access latency to proposes the variable aware Set(VAS)LLC and variable aware Way(VAW).For VAS LLC,this thesis proposes a static page mapping strategy to ensure that the most frequently used virtual pages are mapped to fast partition of LLC.Similarly,for VAW LLC,this thesis proposes a latency-aware LRU replacement strategy to assign the most recently used data to the fast cache way.The experimental results show that the performance of LLC with the optimized method is improved by 39% on average and the power consumption is reduced by 10% on average,compared with the traditional CNFET LLC.Secondly,this thesis proposes a solution to the PV for the CNFET-based non-uniform cache access(NUCA)LLC.For the static non-uniform cache access(S-NUCA),this thesis provides the bank aware static non-uniform cache access(BA-SNUCA),the each bank of the BA-SNUCA is a variable aware cache.The experimental results show that the IPC of the on-chip system with BA-SNUCA can improve 7.5% and the power consumption can reduce 6.8%,compared with the traditional S-NUCA.For dynamic non-uniform cache access(D-NCUA),this thesis proposes a latency-aware migration strategy which can mitigate the frequently used data towards the fast banks.The experimental results show that the IPC of on-chip system with the latency-aware D-NCUA can increase 5.9% on average and the power consumption can cut down 5.3%,compared with the traditional gradual promotion migration strategy.更多还原