【作者】 黄俊；

【导师】 吴建辉；

【作者基本信息】 东南大学 ， 微电子学与固体电子学， 2018， 硕士

【摘要】 现代高速通信系统,比如超带宽无线电、高速串行链路以及以太网收发器等,需要用到中等分辨率以及数百兆采样率的模数转换器(ADC)。常用的高速ADC类型主要有全并行型(Flash)ADC、流水线型(Pipeline)ADC和逐次逼近型(SAR)ADC。其中,SAR ADC因简单紧凑的结构、低功耗、兼容先进工艺以及易于交织的优点被广泛使用。本文面向现代高速通信系统的应用需求,设计一款8位先2位/周期(2bit/cycle)后1位/周期(1bit/cycle)的高速低功耗异步SAR ADC。本文兼顾高速与低功耗设计,同时保证高的有效位数(ENOB)性能。首先,三个比较器与两个电容型数模转换器(DAC)用来实施前4次2bit/cycle转换,极大提升ADC速度;在噪声干扰严重的最后一个1bit/cycle相仅有中间比较器参与,因此ADC对中间比较器噪声要求更高,通过合理分配中间比较器与外侧比较器的功耗,在有效降低整体功耗的同时保证ADC具有更好的ENOB性能;为减小三个比较器间的相对失调,提出一种低功耗的片上外侧比较器后台失调校准方法,该方法以较低的频率在最后一个1bit/cycle相进行,能够跟踪电压、温度的变化且保证高能效;由于采用较大的最低有效位(LSB),本文仅加入1位二进制冗余,为DAC的建立误差以及DAC间的失配提供足够的冗余范围,同时减少总的转换次数以及数字误差校正电路的开销;提出基于中间比较器的带两步加速的异步自时钟控制逻辑,进一步压缩了转换时间,提高ADC的速度上限。本文基于TSMC 40nm CMOS工艺进行SAR ADC的设计,核心版图面积为0.016mm~2,包括片上失调校准电路。后仿结果表明:1.1V电源电压,400MS/s采样率,奈奎斯特输入频率下的ENOB为7.6bit,品质因数(FoM)达56.3fJ/conv.-step;1.25V电源电压,500MS/s采样率,奈奎斯特输入频率下的ENOB为7.6bit,FoM达64.2fJ/conv.-step。仿真结果满足高速低功耗的设计要求。更多还原

【Abstract】 Modern high-speed communication systems such as ultra-wideband radios,high-speed serial links,and Ethernet network transceivers demand medium-resolution analog-to-digital converters(ADCs)with hundreds of MS/s.In contrast with flash and pipeline ADCs,successive-approximation-register(SAR)ADC is widely used due to its simple and compact architecture,low power,well-adapted in advanced processes and easy-interleaved advantage.The main task of this thesis is to design a high-speed and low-power asynchronous SAR ADC with8bit resolution which meets the requirements of above mentioned modern high-speed communication systems.2-then-1bit/cycle SAR ADC architecture is adopted.This thesis takes both high-speed and low-power design into consideration while guaranteeing high ENOB performance.Firstly,three comparators and two capacitive digital-to-analog converters(DACs)are implemented to perform first four2bit/cycle conversions,which significantly improve the speed of ADC.Secondly,only center-comparator is used in the last 1bit/cycle phase where is noisy,which should have better noise performance.By optimizing the power of the three comparators,the overall power can be effectively reduced while ensuring that the ADC has better ENOB performance.Thirdly,to reduce the relative offset error between the three comparators,a low-power on-chip background offset calibration for outer-comparators is proposed,which is performed at a low frequency in the last 1bit/cycle phase,keeping track of the voltage-temperature variations and achieving high-energy-efficiency.Becides,there is only one binary redundant bit in the system due to larger LSB to offer enough redundant range for both DAC settling error and mismatch between DACs,which simultaneously reduce both total cycles and the overhead of digital error correction circuit.Finally,the proposed center-comparator-based asynchronous self-time control scheme with two step acceleration further compresses conversion time,improving the maximum speed of ADC.The presented SAR ADC is implemented in TSMC 40nm CMOS process,which occupies an active area of 0.016mm~2 including on-chip offset calibration circuit.Post-simulation results show that the ADC exhibits a 7.6bit ENOB at Nyquist input frequency when operating at a sampling rate of 400MS/s under a1.1V supply,leading to a FoM of 56.3fJ/conv.-step.Moreover,the ADC achieves a 7.6bit ENOB at Nyquist input frequency and a FoM of 64.2fJ/conv.-step when operating at 500MS/s under a 1.25V supply.Consequently,the results meet the high-speed and low-power design requirements.更多还原