【作者】 马跃；

【导师】 关宝璐；

【作者基本信息】 北京工业大学 ， 集成电路工程（专业学位）， 2018， 硕士

【摘要】 随着集成电路深亚微米技术的快速发展,音频Sigma-Delta ADC在便携式多媒体播放器和手持音频设备中具有广泛的应用。其中高精度Sigma-Delta调制器的低功耗实现成为限制ADC性能的关键。本论文针对Sigma-Delta调制器的高精度和低功耗设计进行了具体研究,并完成了一款Sigma-Delta调制器的原型电路设计。本文首先调研了Sigma-Delta ADC的国内外现状,论述了Sigma-Delta ADC的基本原理及其发展和应用,分析并比较了各种常用结构的特点。根据课题设计要求,利用Matlab Simulink工具对调制器结构进行了行为级建模,在模型中针对实际电路中存在的各种非理性进行了模拟和仿真分析,针对仿真结果进行了参数优化,从而确定了三阶前馈单环单比特量化的Sigma-Delta调制结构。在该结构中,针对调制器中最关键的第一级积分器模块进行了低功耗优化设计:积分器中的核心运算放大器采用功耗效率最高的套筒型共源共栅结构,结合动态功耗匹配技术,能够将运放的功耗降低25%,同时采用开关电容共模反馈电路降低功耗并稳定输出共模电压。后两级积分器同样采用套筒型共源共栅结构,对面积和功耗进行缩减以降低电流消耗。使用电容无源加法器对前馈电路求和,采用动态锁存比较器实现单比特量化。本论文基于SMIC 0.18μm COMS工艺设计了Sigma-Delta调制器的电路原理图,并完成了版图设计和电路后仿真,调制器的面积为0.042mm~2。后仿结果表明:在电源电压为1.8V,过采样为256倍,信号输入频率12.5KHz,幅值为400mV的条件下,SNR达到99.8dB,有效位数达到16.28位,消耗电流为0.83mA,满足了各项设计的指标要求。更多还原

【Abstract】 With the rapid development of integrated deep sub-micron technology,audio Sigma-Delta ADC has a wide range of applications in portable multimedia players and handheld audio devices.The low-power implementation of the high-precision Sigma-Delta modulator has become the key to limiting the performance of the ADC.This paper focuses on the high-precision and low-power design of Sigma-Delta Modulator,and completes a prototype circuit design of Sigma-Delta Modulator.This paper first shows situation of Sigma-Delta ADC at home and aboard.Then,the basic principles of Sigma-Delta ADC and development are introduced.At last,characteristics of various structures are compared.According to the design requirements of the project,using the Matlab Simulink tool to conduct behavioral level modeling of the modulator structure,the third-order feed-forward single-loop quantized Sigma-Delta modulator structure are determined.In this structure,a low-power design is performed for the most critical first-stage integrator module in the modulator:the core amplifier in the integrator employs the most power-efficient dynamic telescopic cascode structure,The dynamic amplifier technology can reduce the power consumption of the amplifier by 25%.At the same time,it uses a switched-capacitor common-mode feedback circuit to reduce power consumption and stabilize the output common-mode voltage.The latter two stage integrators use the same structure as the first stage integrator directly,but reducing the ratio of MOS width to reduce the current consumption.Capacitors and adder are used to sum feed-forward circuits,and dynamic latch comparator used to implement single-bit quantization.This paper designs the schematic diagram of the Sigma-Delta modulator circuit based on the SMIC 0.18μm COMS process and completes the layout design.The total area is 0.042mm~2.The post-simulation result of the Sigma-Delta modulator shows,under the condition that the power supply voltage is 1.8V,oversampling ratio is 256,sampling frequency is 12.288MHz,input signal frequency is 12.5KHz,and the amplitude is 400mV.The effect number of bits reaches 16.28bit,signal noise ratio is99.8dB,and the current consumption is 0.83mA,which satisfies the design requirements.更多还原