【作者】 王超；

【导师】 姚若河； 邝国华；

【作者基本信息】 华南理工大学 ， 工程硕士（专业学位）， 2018， 硕士

【摘要】 随着各类电子行业快速发展,电源管理芯片得到巨大的应用需求,低压差线性稳压器(Low Dropout Regulator,LDO)因结构简单、精度高、响应快速等优点,成为了应用较为广泛的一类。传统LDO在芯片外接一个大电容来提升稳定性和瞬态响应能力,而伴随SoC系统芯片的发展,单个芯片中多个LDO同时供给电源,需要去掉传统LDO的外接电容来减小芯片面积和PCB板面积,提高集成度。因此,无片外电容LDO成为了研究的热点。本文对LDO的稳定性进行了分析,传统LDO去掉接于输出端的片外电容,系统环路的零极点位置会发生改变,不能够保证负载变化时在相应状态下的稳定。针对稳定性问题,通过在传统结构的误差放大器和功率管之间添加输出阻抗非常低的缓冲器,将功率管栅极极点的位置控制在高频范围,忽略该极点对环路稳定性的影响,并采用补偿电容进行频率补偿,保证了足够的相位裕度,实现了LDO在负载工作范围内所有状态下的稳定。此外,传统LDO去掉外接电容,输出端的负载电容较小,在负载瞬态变化时,负载电容上的电荷充放电提供的电流不能够进行足够的补偿,输出电压的过冲和下冲较大,瞬态性能较差。针对瞬态响应问题,本文提出了一种瞬态提升电路。负载的瞬态变化导致LDO输出的瞬态改变,经过反馈会引起误差放大器输出端电压的改变,电路通过检测误差放大器输出端电压的改变,增加对功率管栅极电容的充放电电流,使功率管的状态能够迅速匹配负载,功率管的输出电流对负载进行补偿,系统输出能够快速稳定,提升了LDO瞬态响应的能力。本文电路基于TSMC 0.18μm标准CMOS工艺设计实现,稳定性仿真显示在宽负载范围内环路相位裕度大于60°;输入电压范围为2V~3.6V,输出电压为1.8V,实际最小压差为120mV;负载于1μs内在0和100mA之间变化时,输出过冲和下冲小于41mV。针对主体电路本文进行了版图设计,并对主要性能作后仿,仿真结果显示负载于1μs内在0和100mA之间变化时,输出过冲和下冲小于56mV。更多还原

【Abstract】 With the rapid development of various types of electronic industries,there have been great application requirements for power management chips.Low dropout regulators(LDOs)have become widely used because of their advantages such as simple structure,high precision,and fast response.For a conventional LDO,a large capacitor is added to the outside of the chip to enhance its stability and transient response capability.With the development of SoC system chips,multiple LDOs are used to supply voltages at the same time in one chip,it is necessary to remove the external capacitors of conventional LDOs to reduce chip area and PCB area,improving integration.Therefore,Capacitor-less LDO has become a research hotspot.In this paper,the stabilities of LDOs are analyzed.With the off-chip capacitor connected to the output in conventional LDO being removed,the zero-pole positions of the system loop will change,and it cannot guarantee the stabilities under the corresponding states when the load changes.For the stability problem,the position of the gate pole of the power transistor is controlled in the high frequency range by adding a buffer with a very low output impedance between the error amplifier and the power transistor of the conventional structure,ignoring the influence of the pole on the stability of the loop.And a compensation capacitor is used for frequency compensation to ensure sufficient phase margin and achieve stability of the LDO in all states within the load operating range.In addition,the load capacitor at the output is small with the external capacitor in conventional LDO being removed.When the load transiently changes,the current supplied by the charge and discharge on the load capacitor cannot provide sufficient compensation,and the overshoot and undershoot of the output voltage are large.Poor transient performance.For the transient response problem,a transient enhancement circuit is proposed in this paper.Transient changes in the load causes transient changes in the output of the LDO,and feedback can cause the voltage at the output of the error amplifier to change.The circuit detects the changes of the output voltage of the error amplifier to increase the charge and discharge current to the gate capacitance of the power transistor,so that the state of the power transistor can quickly match the load.The output current of the power transistor compensates the load,and the system output can be quickly stabilized,improving the LDO transient response capability.The circuit is designed based on the TSMC 0.18μm standard CMOS process.The stability simulation shows that the loop phase margin is greater than 60° over a wide load range.the input voltage range is 2V ~ 3.6V,the output voltage is 1.8V,and the actual minimum voltage dropout is 120 mV.When the load changes between 0 and 100 mA within 1μs,the output overshoot and undershoot are less than 41 mV.The layout of the main circuit is designed and the main performances are post-simulated.The simulation result shows that the output overshoot and undershoot are less than 56 mV when the load changes between 0 and 100 mA within 1μs.更多还原