【作者】 王佳；

【导师】 杜永强； 朱泽恩；

【作者基本信息】 东南大学 ， 电子与通信工程（专业学位）， 2017， 硕士

【摘要】 随着3G/LTE/5G的不断发展,无线网络正从普通几个天线的MIMO向大规模MIMO演进,这使得新一代5G系统可以有效利用数字波束形成(DBF)技术实现空间资源灵活调度,由此对多天线间的时间同步性能也提出了新的高精度要求。以5G试验平台中采用的100MHz信号带宽为例考虑,要实现DBF技术,天线间信号的定时误差至少需要控制在一个采样周期内。目前市场上常见的标准时钟同步设备无法满足5G试验平台的高精度要求。因此,本文尝试采用IEEE1588V2时钟同步协议和同步以太网技术相结合的时钟同步方案,致力于研究如何实现5G试验平台对高精度时钟同步的需求。本文首先介绍了时钟同步的基本理论。随后详细介绍了 IEEE1588时钟同步协议和同步以太网技术的相关理论。第三章和第四章则给出了 IEEE1588从时钟的硬件设计和软件设计的具体实现过程。本文设计的嵌入式IEEE1588从时钟同步系统,采用支持IEEE1588协议的PHY芯片DP83640,在MII接口处获取event报文的时间戳,结合物理层的同步以太网技术,可有效提高时钟同步精度,避免了晶振的频率抖动对本地时间的稳定性的影响。最后,本文对IEEE1588从时钟同步系统进行了同步精度测试,分别对普通PTP同步和基于同步以太网的PTP同步进行了测试。结果表明,普通PTP同步随着同步周期的缩短,精度会相应提高,但因为所选取的硬件的限制,同步周期最短为0.0625s,此时同步误差的峰峰值为20ns左右,无法满足5G试验平面对时钟同步精度的要求。在普通PTP同步的基础上,引入同步以太网技术以后,大大提高了系统的时钟同步精度,测试数据表明同步误差的峰峰值可小于1ns。本文的时钟同步方案已成功应用于5G试验平台。更多还原

【Abstract】 With the continuous development of 3G/LTE/5G,wireless network is evolving from ordinary several antennas to large-scale MIMO so that new-era 5G system can effectively use digital beamforming technology to achieve flexible space resource scheduling.As a result,a new requirement of high precision time synchronization is put forward among antennas.In 5G test platform using the 100 MHz signal bandwidth,the signal timing error between antennas needs to be controlled within a sampling period in order to realize DBF technology.Common clock synchronization devices on the market at present cannot meet the precision requirement of 5G test platform.Therefore,this thesis attempts to adopt a clock synchronization scheme that is the combination of IEEE1588V2 clock synchronization protocol and synchronous Ethernet technology to research how to realize the high precision clock synchronization requirement of 5G test platform.Firstly,this thesis introduces the basic theory of clock synchronization.Then it introduces relevant theories of IEEE1588 clock synchronization protocol and synchronous Ethernet.The third and fourth chapters provide the detailed realization process of the hardware and software about the IEEE1588 slave clock system.The embedded IEEE 1588 slave clock synchronization system designed in this thesis,adopting a PHY chip named DP83640 supporting IEEE1588 protocol,achieving event message timestamps at MII interface,combining with synchronous Ethernet technology,can effectively improve the clock synchronization precision and avoid crystal vibration frequency jitter that effects the stability of the local time.Finally,the thesis tests the synchronization accuracy of the IEEE1588 slave clock system,including ordinary PTP synchronization and the other synchronization method based on synchronous Ethernet.The results show that synchronization accuracy will enhance with synchronous cycle shorted in ordinary PTP synchronization.But with the limitation of selection of hardware,the shortest synchronous cycle is 0.0625s.Under this circumstance,the peak-to-peak value of synchronization error is around 20ns,which can’t meet the clock synchronization accuracy requirement of 5G test platform.On the basis of ordinary PTP synchronization,synchronous Ethernet technology promotes the precision of the clock synchronization system a lot.Test data shows that the peak-to peak value of synchronous error is less than 1 ns.In this thesis,the clock synchronization scheme has been successfully applied in 5G test platform.更多还原