【作者】 郭瑞；

【导师】 来逢昌；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2017， 硕士

【摘要】 随着集成电路和航天事业的发展,片上系统(So C)芯片越来越多地被应用在辐射环境中。存储器是So C中的重要组成部分,对存储器进行抗辐射加固是当今存储器的一个重点研究方向。本文采用SMIC0.18μm工艺设计了一个应用于抗辐射So C中的加固SRAM存储器。本文首先分析了单粒子翻转效应、单粒子闩锁效应和总剂量效应,以及常用的加固方法,并针对这三种辐射效应确定了本设计中使用的加固方法。随后根据设计要求进行8Kb存储器的架构设计和时序设计。针对单粒子翻转进行存储单元的电路级加固,采用12管DICE电路结构设计了存储器阵列。然后对存储器的外围电路进行设计和功能仿真,包括行列译码电路、数据输入/输出电路、灵敏放大器和时钟电路。并着重对锁存器型灵敏放大器的结构、功能和性能进行分析。完成了完整的存储器的设计与仿真,本设计中的SRAM存储器工作频率可以达到100MHz。访问时间约为0.926ns,功耗为3.88m W。最后进行版图设计,在版图中使用电源接触和衬底接触对单粒子闩锁效应和总剂量效应进行加固,存储器版图大小为603900.3432μm2。对版图进行了寄生参数提取并进行了后仿真,后仿结果表明存储器功能正确。访问时间为1.21ns,功耗为5.136m W,与前仿结果相差不大。更多还原

【Abstract】 With the development of integrated circuit and aerospace industry,System on Chip(So C)are more and more used in the radiation environment.Memory is an important part of So C,the memory radiation hardening is a key research area of today’s memory.In this paper,a SRAM memory for anti radiation So C is designed by using SMIC0.18 μm process.In this paper,the Single Event Upsets effect,Single Event Latchup effect and Total Ionizing Dose effect,as well as the common hardened methods are analyzed,and the hardened methods used in the design are determined according to the three radiation effects.Subsequently,the architecture design and timing design of 8Kb memory are carried out according to the design requirements.In order to strengthen the circuit level of memory cell for Single Event Upsets,a memory array is designed by using 12-tube DICE circuit.Then,the peripheral circuit of memory is designed and simulated,including row and column decoding circuit,data input /output circuit,sensitive amplifier and clock circuit.The structure,function and performance of latch type sense amplifier are analyzed emphatically.Completed the entire memory design and simulation,the design of the SRAM memory frequency can reach 100 MHz.The access time is about 0.926 ns and the power consumption is 3.88 m W.Finally,the layout design is carried out,and in the layout,the Single Event Latchup and the Total Ionizing Dos are reinforced by power contact and substrate contact,and the memory layout size is 603900.3432μm2.The parasitic parameters are extracted and simulated,the simulation results show that the function of the memory is correct.The access time is 1.21 ns,and the power consumption is 5.136 m W,which is not much different from the previous simulation results.更多还原