【作者】 孙越；

【导师】 樊祥宁； 陈健；

【作者基本信息】 东南大学 ， 工程硕士（专业学位）， 2017， 硕士

【摘要】 随着现代通信技术的飞速发展和通信设备的快速更新,将多种模式的无线通信系统在单个芯片上高度集成已经成为大势所趋,而多模多标准射频收发机是其中至关重要的技术。其中,频率综合器为发射机和接收机两端提供本振信号,对多模式多标准射频收发机具有重要意义。所以,频率综合器性能的好与坏直接关系到整个收发机是否能实现正确的数据通信。本论文设计的分数分频器就是多模多标准频率综合器中至关重要的模块。本文首先对设计的分数分频器进行各模块的详细设计与分析,主要包括三个模块,分别为高速二分频器、0.5步进可编程分频器和△-∑调制器。第一级为高速二分频器,是电路中工作频率最高的模块。高速二分频器采用电流模逻辑,工作频率范围达到lGHz～8GHz,输出为四相正交的本振信号。0.5步进可编程分频器包括相位切换电路和整数可编程分频器两部分。前者主要完成0.5步进,通过切换四分频器输出的八个信号实现0.5的精度。后者控制整数分频比范围,通过将五个2/3分频器级联实现整数分频。另外还在级联中加入了逻辑门,对分频比进行了扩展,实现8-63的分频比范围。△-∑调制器通过半定制的方法实现,其电路采用MASH1-1-1结构并做了改进,增加了输出序列长度,减小了小数杂散。本分数分频器设计采用TSMC0.18μmRFCMOS工艺,整体的版图面积为950μm×530μm(包含焊盘)。后仿真结果表明:在1.8V电源电压下,分数分频器能够实现0.5GHz～8.6GHz频率范围内正常分频,分频比范围为65～502,总电流9.10mA,满足设计指标。更多还原

【Abstract】 With the rapid development of modem comunication technology and the quick update of communication equipment,a signal chip with different wireless standards has become the trend and the Multi-Mode Multi-Standard RF transceiver is a crucial technology.The frequency synthesizer provides the local oscillator signal to both transmitter and receiver ends.Thus,the RF transceiver machine has important significance.Therefore,the quality of frequency synthesizer is directly related to the performance of the transceiver.The design of a Fractional-N Frequency Divider(FNFD)in this thesis is of vital importance to the multi-standard Fractional-N Frequency Synthesizer(FNFS).A system framework of wideband FNFS is firstly proposed in this thesis.On this basis,the detailed design and analysis of the FNFD is intoduced,including high-speed divide-by-2 circuit,programmable frequency dividerwith 0.5 step size and a △-∑ modulator.The first high-speed divide-by-2 circuit works at the highest frequency and it uses SCL(Source Coupled Logic)structure.It has a very wide operating frequency range(1GHz to 8GHz)and generates four orthogonal local oscillating signals.The programmable frequency divider includes a phase switching circuit and an integer-N programmable frequency divider.The former mainly completes 0.5step size by switching the output of the eight signals.The latter controls the integer frequency division.It is achieved by adivide-by-2/3 circuit chain and its frequency division ratio can be extended by logic gates.The integer-N programmable frequency divider can generate programmable division ratio from 8 to 63.The △-∑ modulator is devised with semi-custom design flow,adopting the MASH 1-1-1 structure and improved.Therefore,the output sequence length is improved and the fractional spurs is reduced.The FNFD is implemented in TSMC 0.18μm RF CMOS process,occupying a chip area of 950μm×530μm.The post simulation results show that under 1.8V supply voltage,the FNFD can correctly divide the input signal within 0.5GHz to 8.6GHz,the frequency division ratio ranges from 65 to 502 and the total current consumption is 9.10 mA.更多还原