【作者】 雷旭；

【导师】 刘洋；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2017， 硕士

【摘要】 频率合成器作为高速串口通信和射频无线收发器中的重要单元模块,其主要作用是产生无线收发机进行上、下变频所必需的本振信号。本振信号决定收发机的变频信号,本振信号的理想程度决定了收发机的性能优劣。频率合成器为收发机系统提供本振信号,其输出信号的频谱纯净度直接决定收发机的频率稳定度,输出频率范围直接决定收发机的频率收发范围,频率精度决定收发机最小信道宽度。因此较低的杂散、较大的输出频率范围和较高的频率精度成为设计频率合成器的重要性能指标。本论文设计了一款高精度频率合成器芯片,采用Delta-sigma小数分频结构,产生范围为810MHz~950 MHz的输出频率。首先基于Matlab和Simulink工具对频率合成器进行系统级建模,包括子模块建模、开环建模和闭环建模,在对子模块建模时,分别在鉴频鉴相模块、电荷泵模块、环路滤波模块和压控振荡器这些子模块的理想模型中,添加频率合成器的噪声模型,模拟实际电路,得到优化的环路参数;随后基于Cadence Spectre设计平台,参考系统级建模参数,对单个模块进行晶体管级电路搭建与仿真,包括鉴频鉴相器、电荷泵、环路滤波器、压控振荡器、可编程分频器和Delta-sigma调制器,其中Delta-sigma调制器用于实现小数分频,降低电路对参考信号的频率要求;最后采用开环自动频率校正技术,在小数分频锁相环电路的基础上,加入自动频率校正模块,完成调谐曲线的快速切换。相较于传统锁相环频率合成器,本频率合成器在扩展输出频率范围的基础上,实现了锁相环频率合成器的快速锁定。本论文设计的小数分频频率合成器芯片在GMSC 0.18μm工艺下流片,并根据高频电子线路布局布线规则设计PCB板。小数分频频率合成器器测试结果如下:功耗91mW、信道宽度20MHz、输出频率范围810MHz-950MHz、1MHz频偏处的相位噪声为-97.8dBc/Hz@1MHz、频率切换时间小于60μs。芯片最终的版图面积为1640μm×1736μm。更多还原

【Abstract】 Frequency synthesizer as a high-speed serial communication and radio frequency radio transceiver in the important unit module,its main role is to generate the wireless transceiver for the upper and lower frequency conversion of the local oscillator signal.The local oscillator signal determines the frequency conversion signal of the transceiver,the ideal degree of the local oscillator signal determines the performance of the transceiver.The frequency synthesizer provides the local oscillator signal for the transceiver system.The spectral purity of the output signal directly determines the frequency stability of the transceiver.The output frequency range directly determines the frequency transceiver range of the transceiver.The frequency accuracy determines the minimum channel width of the transceiver.So the lower spurious,the larger output frequency range and the higher frequency accuracy become the design frequency synthesizer important performance index.This paper designs a Delta-sigma fractional-frequency synthesizer chip with output frequency range of 810 MHz to 950 MHz.Firstly,the frequency synthesizer is modeled on the frequency synthesizer based on Matlab and Simulink tools,including sub-module modeling,open-loop modeling and closed-loop modeling.In modeling the sub-modules,the frequency module,The loop filter module and the voltage-controlled oscillator,the noise model of the frequency synthesizer is added to simulate the actual circuit and the optimized loop parameters are obtained.Then,based on the Cadence Specter design platform,the system-level modeling parameters,Including a frequency discriminator,a charge pump,a loop filter,a voltage controlled oscillator,a programmable divider and a Delta-sigma modulator,in which the Delta-sigma modulator is used for a single module.Finally,the open-loop automatic frequency correction technique is used to add the automatic frequency correction module on the basis of the fractional-frequency phase-locked loop circuit to complete the fast switching of the tuning curve.Compared with the traditional PLL frequency synthesizer,this frequency synthesizer realizes the fast locking of the PLL synthesizer based on the extended output frequency range.In this paper,the frequency synthesizer chip is designed in the GMSC 0.18μm process,and the PCB board is designed according to the high-frequency electronic circuit layout and routing rules.Frequency synthesizer test results are as follows: power consumption 91 mW,channel width 20 MHz,the output frequency range 810MHz-950 MHz,1MHz frequency offset phase noise of-97.8d Bc / Hz@1MHz,frequency switching time is less than 60μs.The final layout area of the chip is 1640μm × 1736μm.更多还原