【作者】 张国栋；

【导师】 张齐军； 李迅；

【作者基本信息】 天津大学 ， 集成电路工程（专业学位）， 2016， 硕士

【摘要】 随着半导体工艺的快速发展,大规模集成电路系统的集成度和复杂度越来越高,设计难度越来越大。从零开始设计这样一个大型的电路系统几乎是不可能的。由于能有效地提高设计效率、降低市场风险以及减少研发费用等,在系统设计中使用自定义或者第三方知识产权(IP)核成为标准的模式。由于具有可编程性、设计成本低以及性能优异等特点,现场可编程门阵列(FPGA)已经成为一种主流的设计平台。随着FPGA在电子系统设计中的广泛应用,设计者越来越重视基于FPGA的电路设计的知识产权(IP)保护问题。本文基于环形振荡器型物理不可克隆函数(RO PUF)提出了一种新型的FPGA IP保护机制,在IP设计中嵌入PUF逻辑,以限制IP设计被复制和滥用。实际应用中,在FPGA上实现RO PUF面临的主要挑战包括:1)RO PUF电路的面积消耗很大;2)有限的逻辑资源使得激励响应对数量有限,限制了该IP保护方法可以验证FPGA IP核的数量。为了解决这些问题,本文提出了一种逻辑混合技术。该技术把PUF逻辑和正常电路逻辑在FPGA实现中混合起来,以减少PUF的电路面积消耗。此外,本文采用了一种后处理方法,极大地增加了所设计RO PUF的激励响应对数量。实验结果显示,可靠性、随机性和独特性分别为99.97%、50.37%、49.83%。同时,消耗的硬件资源比其他同等性能的PUF少了45%。更多还原

【Abstract】 With the rapid development of semiconductor technology,the integration and complexity of the large scale integrated circuit system is higher and higher,and design is becoming more and more difficult.Developing such systems from scratch has become an insurmountable task for most developers.A system-level design approach reusing custom and third-party intellectual property(IP)modules has become a standard procedure.With its reprogrammability,low design cost and excellent capacity,field programmable gate array(FPGA)has become a popular design platform.As FPGAs have been adopted in many electronic system designs,IP protection of FPGA implementations has become one of the major concerns of the designers.This thesis proposes a novel RO PUF-based FPGA IP protection mechanism which embeds PUF logic in the IP core designs in order to efficiently protect IPs from being cloned and illegal usage.Integrating RO PUF into FPGA implementations for practical applications still faces major challenges,including 1)it always introduces considerable hardware overheads;and 2)the limited set of challenge-response pairs(CRPs)due to limited circuit resources may not authenticate a large population of FPGA IP cores with less error.To address these issues,this thesis firstly proposes an effective technique,logic fusion.It combines the RO logic of the PUF with the normal circuit logic,without increasing logic resource usage in FPGA.Secondly,a post-processing procedure is exploited to expand the set of CRPs from the designed RO PUF.Experimental results show that the reliability,randomness and uniqueness metrics of the designed RO PUF are 99.97%,50.37% and 49.83%,respectively.Compared with the existing RO PUF design techniques,the area overhead can be reduced by 45% with the same performance.更多还原