【作者】 陈琛；

【导师】 何乐年； 奚剑雄；

【作者基本信息】 浙江大学 ， 电气工程， 2017， 硕士

【摘要】 低压差线性稳压器(low-dropout regulator,LDO)具有结构简单、低噪声、低功耗以及封装尺寸小等突出优点,在便携式电子产品中作为电源转换电路得到广泛的应用。无片外电容LD0不需要外接特定的电容,也不需增加额外引脚,减小了芯片和PCB面积,从而成为近年来研究的热点。本文着重研究与设计超低功耗无片外电容LDO,首先对实现超低功耗、无片外电容LDO的几个关键问题进行了研究分析,主要针对超低功耗LDO如何分配电流、增强摆率以及无片外电容LDO如何补偿频率、改善瞬态特性等作出研究。并对低电压带隙基准的设计、高摆率缓冲器的设计、频率补偿方式的分析,以及负载调整率的改善四个方面进行了深入的理论研究和探讨。最后利用上述的理论研究,设计了输出电压为1.5 V,最大输出电流为1.5 mA,静态电流为881 nA的无片外电容LDO。该LDO主环路采用三级运放结构,将带动态偏置并联反馈结构的缓冲器作为中间级驱动PMOS功率管。使用嵌套密勒补偿方式(NMC),将低频主极点放置在第一级输出,将缓冲器输出极点和LD0输出极点作为次极点构成极点-极点追踪。芯片采用GSMC公司的130 nmCMOC工艺模型设计并经流片测试。测试结果表明:在1.6～4.2V输入电压下,输出1.5V电压,最大输出电流为1.5mA时静态电流小于881 nA。当负载电流在100 ns内由1.5 mA到0跳变时,输出电压变化小于95 mV;当电源电压在0.5 V范围内跳变时,输出电压变化小于36 mV。测试结果验证了以上设计。更多还原

【Abstract】 Low-dropout regulator(LDO)has the advantages of simple structure,low noise,low power consumption and small package size advantages and is widely used in portable electronic products as a power conversion circuit.No off-chip capacitor LDO does not need to be connected to a specific capacitance,and does not need to increase additional pins,so it could reduce the chip and PCB area,and is becoming a hot spot of present research.This paper focuses on the research and design of ultra low power LDO with no off-chip capacitor.Firstly,several key problems of ultra low power LDO with no off-chip are discussed.To ultra low power LDO,it is mainly focus on how to distribute quiescent current;how to enhance slew rate.To LDO with no off-chip capacitor,it is mainly about how to compensate frequency and how to improve transient characteristics.Besides,the design of the low voltage bandgap reference,the design of high slew rate buffer,the analysis of the frequency compensation and the improvement of the load regulation are also discussed.Finally,an ultra low power LDO with no off-chip capacitor is design based on the previous theoretical study.The 1.5-V 1.5-mA low-dropout regulator(LDO)with no off-chip capacitor and 881 nA quiescent current is designed and implemented by using GSMC 130 nm CMOS process.The LDO main loop adopts three-stage amplifier structure,with dynamically-biased shut feedback structure as an intermediate buffer for driving the pass device.By using nested Miller compensation(NMC),it puts the dominant pole on the output of the first-stage and the non-dominant poles on the output of the buffer and the output of the pass device.Thus,the non-dominant poles realize pole-pole tracking frequency compensation.Measured results shown that the output voltage was stable at 1.5V when its supply was set to be from 1.6 V to 4 V.The quiescent current was less than 881 nA at 1.5 mA output current.As the load current decreased from 1.5 mA to 0 within 100 ns,the ripple of output voltage was less than 95 mV;and when the supply changed within 0.5 V,the ripple of output voltage was less than 36 mV.The designed circuit was validated by the results of the chip test.更多还原