【作者】 苏杭；

【导师】 王明江；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2015， 硕士

【摘要】 TFET作为新型的低功耗器件,物理结构上采用源漏区非对称性掺杂,通过外加栅电压控制能带偏移,进而利用隧道击穿原理实现器件工作。与传统漂移扩散机制MOSFET器件相比,TFET器件的亚阈值斜率能够突破60m V/dec的限制,能够在较低电源电压下获得更大的电流开关比,从而实现超低功耗的目标。数字标准单元库是集成电路设计自动化的关键,是衔接前端设计与后端物理实现的桥梁。本文在基于传统MOSFET建库技术基础上,探究了TFET应用的研究方向,将TFET器件应用于数字标准单元库设计上。在已有技术的基础上,利用TFET器件模型,进行了相关研究,并在单元设计、版图规划和器件检测方面取得一定成果。基于传统工艺的MOSFET器件,进行了建库工作,包含库单元的原理图提取及优化,特性仿真和版图绘制,并利用已有的库单元,完成整体的建库流程,包含最重要的各类库文件生成及相应脚本文件编写。在单元设计中,针对单元的组合逻辑和时序逻辑电路进行深入研究,并结合TFET器件模型,对传输门逻辑对整体电路的设计影响进行分析,进而对比选择适合TFET器件的电路设计结构;另外,根据现有的模型兼容性问题,设计了测试触发器电路建立时间和保持时间的双时钟边沿测试电路。在版图规划方面,依据流片测试的版图模型并结合单元库设计方案,对单元版图进行了规划,并针对TFET器件的版图检测进行研究,修改了相应DRC检测规则使之能够针对TFET器件的特殊结构进行检测,其中包含针对一般类型的TFET器件,以及包含Pocket结构和Underlap结构的特殊类型TFET器件。更多还原

【Abstract】 To be one new shape of lower power consumption devices, TFET use the asymmetrical doping of source and drain to achieve energy band offsets, which penetrated the tunnel device working principle. TFET ’s sub-threshold slope can be able to break through the 60 mv/dec limits, which means it can get greater switch current ratio, so as to achieve the goal of ultra low power consumption.Digital standard cell library(SCL) is the key of IC automation, bridging the physical realization and code design. Based on MOSFET SCL technology, this paper has research the develop direction of TFET, and research the method to apply TFET into the digital standard cell library. On the basis of existing technology, and using the specific TFET model provided by University of Notre Dame, we carried out relevant research on library unit design, layout plans and device detection.Based on traditional MOSFET devices, we carried out the digital standard cell library design, which contains the library unit schematic extraction and optimization, simulation, and layout design. In addition, we complete the process of building SCL, includes the most important type of library files and have wrote the corresponding scripts of the building process by using the existing library units.Under in-depth study of the combinational and sequential logic circuits, also the TFET device models, we select specific architecture of the unit circuit to avoid the effect of the TFET passing gate in the unit design. In addition, considering the compatibility issues of existing models, we designed an implemented circuit to test trigger time and hold time by using double clock edge.We also planned the cell layout, which based on the SCL rules and the specific layout model which have be tape-out tested. Then we researched on the DRC rules of the TFET layout, to achieve the goal of DRC testing of general TFET structure and special TFET structure which contains Pocket and Underlap structures.更多还原